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a
Active Energy Metering IC
with Serial Interface
ADE7756*
FEATURES
High Accuracy, Supports IEC 687/1036
Less than 0.1% Error over a Dynamic Range of 1000 to 1
An On-Chip User Programmable Threshold for Line
Voltage SAG Detection and PSU Supervisory
The ADE7756 Supplies Sampled Waveform Data
(20 Bits) and Active Energy (40 Bits)
Digital Power, Phase and Input Offset Calibration
An On-Chip Temperature Sensor ( 3 C Typical after
Calibration)
An SPI-Compatible Serial Interface
A Pulse Output with Programmable Frequency
An Interrupt Request Pin (IRQ) and Status Register
Provide Early Warning of Register Overflow and
Other Conditions
Proprietary ADCs and DSP Provide High Accuracy
over Large Variations in Environmental Conditions
and Time
Reference 2.4 V 8% (20 ppm/ C Typical) with External
Overdrive Capability
Single 5 V Supply, Low Power (25 mW Typical)
The ADE7756 contains a sampled Waveform register and an
Active Energy register capable of holding at least five seconds of
accumulated power at full load. Data is read from the ADE7756
via the serial interface. The ADE7756 also provides a pulse output
(CF) with a frequency that is proportional to the active power.
In addition to real power information, the ADE7756 also provides
system calibration features, i.e., channel offset correction, phase
calibration, and power calibration. The part also incorporates a
detection circuit for short duration low voltage variations or sags.
The voltage threshold level and the duration (in number of half-
line cycles) of the variation are user programmable. An open drain
logic output ( SAG ) goes active low when a sag event occurs.
A zero crossing output (ZX) produces an output that is synchro-
nized to the zero crossing point of the line voltage. This output can
be used to extract timing or frequency information from the line.
The signal is also used internally to the chip in the calibration
mode. This permits faster and more accurate calibration of the
real power calculation. This signal is also useful for synchronization
of relay switching with a voltage zero crossing, thus improving
the relay life by reducing the risk of arcing.
The interrupt request output is an open drain, active low logic
output. The IRQ output will become active when the accumu-
lated real power register is half-full and also when the register
overflows. A status register indicates the nature of the interrupt.
The ADE7756 is available in 20-lead DIP and 20-lead
SSOP packages.
GENERAL DESCRIPTION
The ADE7756 is a high-accuracy electrical power measurement
IC with a serial interface and a pulse output. The ADE7756
incorporates two second-order sigma-delta ADCs, reference
circuitry, temperature sensor, and all the signal processing
required to perform active power and energy measurement.
FUNCTIONAL BLOCK DIAGRAM
AV DD
RESET
DV DD
DGND
PGA
MULTIPLIER
HPF1
MULTIPLIER
LPF2
ADE7756
ZX
V1P
V1N
ADC
SAG
TEMP
SENSOR
APGAIN[11:0]
APOS[11:0]
PHCAL[5:0]
V2P
V2N
ADC
DFC
2.4V
REFERENCE
4k
ADE7756 REGISTERS
AND
SERIAL INTERFACE
CF
LPF1
CFDIV[11:0]
AGND
REF IN/OUT
DIN DOUT SCLK CS
IRQ
CLKIN
CLKOUT
* U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
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ADE7756
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
ADE7756–SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8
PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8
POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8
ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13
LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14
Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Using the ADE7756 Interrupts with an MCU . . . . . . . . . 15
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16
ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16
Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . . 18
Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . 20
ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . . 21
ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . 22
Integration Times under Steady Load . . . . . . . . . . . . . . . 23
POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . . 23
ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . . 23
ENERGY CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . 24
CALIBRATING THE ENERGY METER . . . . . . . . . . . . . 24
Calculating the Average Active Power . . . . . . . . . . . . . . . 24
Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . . 24
Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . 25
SUSPENDING THE ADE7756 FUNCTIONALITY . . . . 26
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 29
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 29
Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt Status Register (04H)/Reset Interrupt
Status Register (05H) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32
–2–
REV. 0
ADE7756
SPECIFICATIONS 1
Parameter
(AV DD = DV DD = 5 V
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,
T MIN to T MAX = –40
C to +85
C, unless otherwise noted.)
A Version B Version Unit
Test Conditions/Comments
ENERGY MEASUREMENT ACCURACY
Measurement Bandwidth
14
14
kHz
CLKIN = 3.579545 MHz
Measurement Error 1 on Channel 1
Channel 2 = 300 mV rms/60 Hz, Gain = 2
Channel 1 Range = 1 V Full Scale
Gain = 1
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 2
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 4
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 8
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 16
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Channel 1 Range = 0.5 V Full Scale
Gain = 1
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 2
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 4
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 8
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 16
0.2
0.2
% typ
Over a Dynamic Range 1000 to 1
Channel 1 Range = 0.25 V Full Scale
Gain = 1
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 2
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 4
0.1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 8
0.2
0.2
% typ
Over a Dynamic Range 1000 to 1
Gain = 16
0.2
0.2
% typ
Over a Dynamic Range 1000 to 1
Phase Error 1 Between Channels
±0.05
±0.05
° max
Line Frequency = 45 Hz to 65 Hz, HPF On
AC Power Supply Rejection 1
AV DD = DV DD = 5 V + 175 mV rms/120 Hz
Output Frequency Variation (CF)
0.2
0.2
% typ
Channel 1 = 20 mV rms/60 Hz, Gain = 16,
Range = 0.5 V
Channel 2 = 175 mV rms/60 Hz, Gain = 4
DC Power Supply Rejection 1
AV DD = DV DD = 5 V ± 250 mV dc
Output Frequency Variation (CF)
±0.3
±0.3
% typ
Channel 1 = 20 mV rms/60 Hz, Gain = 16,
Range = 0.5 V
Channel 2 = 175 mV rms/60 Hz, Gain = 4
ANALOG INPUTS
See Analog Inputs Section
Maximum Signal Levels
± 1
± 1
V max
V1P, V1N, V2N and V2P to AGND
Input Impedance (dc)
390
390
kΩ min
Bandwidth
14
14
kHz
CLKIN/256, CLKIN = 3.579545 MHz
Gain Error 1, 2
External 2.5 V Reference, Gain = 1 on
Channel 1 and 2
Channel 1
Range = 1 V Full Scale
± 4
± 4
% typ
V1 = 1 V dc
Range = 0.5 V Full Scale
± 4
± 4
% typ
V1 = 0.5 V dc
Range = 0.25 V Full Scale
± 4
± 4
% typ
V1 = 0.25 V dc
Channel 2
± 4
± 4
% typ
V2 = 1 V dc
Gain Error Match 1
External 2.5 V Reference
Channel 1
Range = 1 V Full Scale
±0.3
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Range = 0.5 V Full Scale
±0.3
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Range = 0.25 V Full Scale
±0.3
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Channel 2
±0.3
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Offset Error 1
Channel 1
±20
±20
mV max
Range = 1 V, Gain = 1
Channel 2
±20
±20
mV max
Gain = 1
WAVEFORM SAMPLING
Sampling CLKIN/128, 3.579545 MHz/128 =
27.9 kSPS
Channel 1
See Channel 1 Sampling
Signal-to-Noise Plus Distortion
62
62
dB typ
700 mV rms/60 Hz, Range = 1 V, Gain = 1
Bandwidth (–3 dB)
14
14
kHz
CLKIN = 3.579545 MHz
Channel 2
See Channel 2 Sampling
Signal-to-Noise Plus Distortion
52
52
dB typ
300 mV rms/60 Hz, Gain = 2
Bandwidth (–3 dB)
156
156
Hz
CLKIN = 3.579545 MHz
REV. 0
–3–
104209201.002.png
ADE7756–SPECIFICATIONS
Parameter
A Version B Version Unit
Test Conditions/Comments
REFERENCE INPUT
REF IN/OUT Input Voltage Range
2.6
2.6
V max
2.4 V + 8%
2.2
2.2
V min
2.4 V – 8%
Input Capacitance
10
10
pF max
ON-CHIP REFERENCE
Nominal 2.4 V at REF IN/OUT Pin
Reference Error
±200
±200
mV max
Load Current
10
10
µA max
Output Impedance
4
4
kΩ min
Temperature Coefficient
±20
±20
ppm/°C typ
±80
ppm/°C max
CLKIN
Note All Specifications CLKIN of 3.579545 MHz
Input Clock Frequency
10
10
MHz max
1
1
MHz min
LOGIC INPUTS
RESET , DIN, SCLK, CLKIN and CS
Input High Voltage, V INH
2.4
2.4
V min
DV DD = 5 V ± 5%
Input Low Voltage, V INL
0.8
0.8
V max
DV DD = 5 V ± 5%
Input Current, I IN
± 3
± 3
µA max
Typically 10 nA, V IN = 0 V to DV DD
Input Capacitance, C IN
10
10
pF max
LOGIC OUTPUTS
SAG and IRQ
Open Drain Outputs, 10 kΩ Pull-Up Resistor
Output High Voltage, V OH
4
4
V min
I SOURCE = 5 mA
Output Low Voltage, V OL
0.4
0.4
V max
I SINK = 0.8 mA
ZX and DOUT
Output High Voltage, V OH
4
4
V min
I SOURCE = 5 mA
Output Low Voltage, V OL
0.4
0.4
V max
I SINK = 0.8 mA
CF
Output High Voltage, V OH
4
4
V min
I SOURCE = 5 mA
Output Low Voltage, V OL
0.4
0.4
V max
I SINK = 7 mA
POWER SUPPLY
For Specified Performance
AV DD
4.75
4.75
V min
5 V – 5%
5.25
5.25
V max
5 V + 5%
DV DD
4.75
4.75
V min
5 V – 5%
5.25
5.25
V max
5 V + 5%
AI DD
3
3
mA max
Typically 2.0 mA
DI DD
4
4
mA max
Typically 3.0 mA
NOTES
1 See Terminology section for explanation of specifications.
2 See plots in Typical Performance Characteristic curves.
3 See Analog Inputs section.
Specifications subject to change without notice
–4–
REV. 0
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ADE7756
TIMING CHARACTERISTICS 1, 2
Parameter
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, T MIN to T MAX = –40
C to +85
C, unless otherwise noted.)
A, B Versions
Unit
Test Conditions/Comments
Write Timing
t 1
20
ns (min) CS falling edge to first SCLK falling edge.
t 2
150
ns (min)
SCLK logic high pulsewidth.
t 3
150
ns (min)
SCLK logic low pulsewidth.
t 4
10
ns (min)
Valid Data Setup time before falling edge of SCLK.
t 5
5
ns (min)
Data Hold time after SCLK falling edge.
t 6
6.4
µs (min)
Minimum time between the end of data byte transfers.
t 7
4
µs (min)
Minimum time between byte transfers during a serial write.
t 8
100
ns (min) CS Hold time after SCLK falling edge.
Read Timing
t 9
4
µ
s (min)
Minimum time between read command (i.e., a write to Communication
Register) and data read.
t 10
4
µ
s (min)
Minimum time between data byte transfers during a multibyte read.
t 11 3
30
ns (min)
Data access time after SCLK rising edge following a write to the
Communications Register.
t 12 4
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t 13 4
100
ns (max)
Bus relinquish time after rising edge of CS .
10
ns (min)
NOTES
1 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2 See timing diagram below and Serial Interface section of this data sheet.
3 Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.
4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured
number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics
is the true bus relinquish time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200
A
I OL
TO
OUTPUT
PIN
2.1V
C L
50pF
1.6mA
I OH
Figure 1. Load Circuit for Timing Specifications
t 8
CS
t 1
t 2
t 3
t 7
t 6
SCLK
t 4
t 5
DIN
1
00
A4 A3 A2 A1 A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS
t 1
t 9
t 10
t 13
SCLK
DIN
A4 A3 A2 A1 A0
000
t 11
t 11
t 12
DOUT
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
REV. 0
–5–
(AV DD = DV DD = 5 V
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