GSM Direct Conversion Receiver

ECE6420 Design Project 2

Dec. 11. 2000

Group 1

Kyong-Pil Jeong

Hoon Lee

MoonKyun Maeng

YoungCheol Park

Simon Singh

1. Executive Summary

For our design, we choose the aggressive target of –107dBm as the reference sensitivity.  At the same time, we used the simple receiver architecture shown in figure 1 with the gain and NF values. Our design was successful. As illustrated, in the rightmost column of the table below, we got superb performance.

For our performance, it is noteworthy to mention three points. Foremostly, we exceeded even the manufacturer specification for reference sensitivity with value of  –107dBm. Secondly, in the case of C/(N+I) for BER performance, we got a performance four times better than the required specification. That is, 9dBmin as required versus our 15dBmin that we achieved. Thirdly, we achieved a dynamic range six times better than required. That is, the required 87dB versus the 95dB for our receiver design.  

2. Key System Calculations

Prior to the design of the system level blocks, we need to determine the overall system specifications as referred to the input. The relevant parameters are the noise figure(NF), the input third intercept point(IIP3), and the 1dB compression point(P-1dB). For all our calculations, we use the ambitious specification for the reference sensitivity of –107dBm.

              We have decided not to describe the routine equations and formulas for calculating the above parameters. (Every RF engineer knows this standard stuff.)              In short, the relevant values are as follows.

3. Receiver Architecture

We choose a simple, though elegant receiver architecture as illustrated below.

Figure 1. Block diagram of GSM Direct Conversion Receiver

To implement this we had to be innovative as well as persistent. In this pursuit, we set four aggressive goals for our design framework. There are listed below for ease of reading.

Aggressive Design Approach

·         Less than 6dB noise figure (4.5dB NF achieved)

-          Used low noise RF front-end (NF = 2.3dB)

·         More than 91dB dynamic range (95dB DR achieved)

-          Used two variable gain stages (PGA and RF front-end)

-          Total of 99dB programmable gain range

·         Better than 9dB C/(N+I) for BER performance

-          15dB minimum

-          Used 9th order LPF

-          Achieved 85dB attenuation at 600KHz

·        Implement with fewest components

-          Used five components (excluding ADC and LO)

Firstly, we wanted our RF front-end to be ultra low noise – we obtained NF=4.5dB.

Secondly, we targeted for a generous dynamic range and obtained the figure of 95dB.

Thirdly, we wanted to do better than the specified 9dB C/(N+I) for BER performance. Once again, with some muscle and ingenuity we got the 15dB as our minimum value. We did this by designing a 9th order LPF.

For our fourth design prong, we wanted to use the fewest components. We used just five pieces. This juncture brings us to the details of our components.

4. Description and specifications of the components

Our five components are listed below for ease of reading, followed by a brief description of each.

Components Selected

•                   RF Front End (LNA + Mixer) in BiCMOS

                              (IEEE2000 CICC) 

                            Low power consumption (21.5mW)

                            Variable gain control (-2~14dB)

                              High IIP3 (-7.5 dBm for low gain mode)

                            Superb LO-to-RF isolation (>68dB)

                            Tiny Size (3.5 mm2 chip area )

•                   Transmit/Receive Switch -- General RF Switch

                            RF2436 -- RFMD (GaAs MESFET)

                            Low current consumption

                            Low insertion loss (0.5 dB)

              Frequency of 2.5GHz

•                   Band Select Filter -- GSM Application

                            Part# 855820 -- SAWTEK

                            Excellent out-of-band attenuation

                            30dB minimum attenuation

•                   Low Pass Filter

                            9th order Butterworth implementation

              High out-of-channel attenuation (-85dB at 600kHz)

•                   PGA -- Baseband  programmable gain amplifier

                            RF2670 -- RFMD

                            Wide gain control range (70dB gain range)

                            I/Q baseband receivers 

•                   ADC --   8 bit ADC with 1MSPS

                            AD7827 -- Analog Devices 

                            Low power consumption (24mW)

                            High Speed (420nsec max)

              48dB SNR

1. RF Front-End

RF Front-End is most crucial for us. Given our architecture, the RF front end makes or breaks the whole system ---it is the deciding component. To find such a “show-case” component, we carried out an elaborate research of parts built by the analog/RF manufacturers as well as chip implementations within academic research journals. We eventually settled on the RF front end designed and built by the Electronic Circuit group at Helsinki University of Technology in collaboration with Nokia. The block diagram of the RF front-end (figure 2) and the circuits for dual-mode LNA (figure 4) and down conversion mixer (figure 5) are shown below. 

Figure 2. Block Diagram of RF Front-End

Figure 3. Chip Microphotograph

Figure 4. Dual Mode LNA

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