BUK9605-30A_2.pdf

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Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9605-30A
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V DS
Drain-source voltage
30
V
mounting. Using ’ trench ’ technology
I D
Drain current (DC)
75
A
the device features very low on-state
P tot
Total power dissipation
230
W
resistance. It is intended for use in
T j
Junction temperature
175
˚C
automotive and general purpose
R DS(ON)
Drain-source on-state
switching applications.
resistance
V GS = 5 V
5
m
W
V GS = 10 V
4.6
m
W
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
d
1
gate
mb
2
drain
(no connection possible)
g
3
source
2
mb drain
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V DS
Drain-source voltage
-
-
30
V
V DGR
Drain-gate voltage
R GS = 20 k
W
-
30
V
±
V GS
Gate-source voltage
-
-
10
V
±
V GSM
Non-repetitive gate-source voltage t p £
50
m
S
-
15
V
I D
Drain current (DC)
T mb = 25 ˚C
-
75
A
I D
Drain current (DC)
T mb = 100 ˚C
-
75
A
I DM
Drain current (pulse peak value)
T mb = 25 ˚C
-
400
A
P tot
Total power dissipation
T mb = 25 ˚C
-
230
W
T stg , T j
Storage & operating temperature
-
- 55
175
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R th j-mb
Thermal resistance junction to
-
-
0.65
K/W
mounting base
R th j-a
Thermal resistance junction to
Minimum footprint, FR4
50
-
K/W
ambient
board
August 1999
1
Rev 1.100
22888807.005.png 22888807.006.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9605-30A
Logic level FET
STATIC CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V (BR)DSS
Drain-source breakdown
V GS = 0 V; I D = 0.25 mA;
30
-
-
V
voltage
T j = -55˚C
27
-
-
V
V GS(TO)
Gate threshold voltage
V DS = V GS ; I D = 1 mA
1
1.5
2.0
V
T j = 175˚C
0.5
-
-
V
T j = -55˚C
-
-
2.3
V
I DSS
Zero gate voltage drain current V DS = 30 V; V GS = 0 V;
-
0.05
10
m
A
T j = 175˚C
-
-
500
m
A
I GSS
Gate source leakage current
V GS =
±
10 V; V DS = 0 V
-
2
100
nA
R DS(ON)
Drain-source on-state
V GS = 5 V; I D = 25 A
-
4.3
5
m
W
resistance
T j = 175˚C
-
-
9.3
m
W
V GS = 10 V; I D = 25 A
-
3.9
4.6
m
W
V GS = 4.5 V; I D = 25 A
-
-
5.4
m
W
DYNAMIC CHARACTERISTICS
T mb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
C iss
Input capacitance
V GS = 0 V; V DS = 25 V; f = 1 MHz
-
6500 8600
pF
C oss
Output capacitance
-
1500 1800
pF
C rss
Feedback capacitance
-
1000 1350
pF
t d on
Turn-on delay time
V DD = 30 V; R load =1.2
W
;
-
45
65
ns
t r
Turn-on rise time
V GS = 5 V; R G = 10
W
-
220
330
ns
t d off
Turn-off delay time
-
435
600
ns
t f
Turn-off fall time
-
320
450
ns
L d
Internal drain inductance
Measured from upper edge of drain
-
2.5
-
nH
tab to centre of die
L s
Internal source inductance
Measured from source lead
-
7.5
-
nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I DR
Continuous reverse drain
-
-
75
A
current
I DRM
Pulsed reverse drain current
-
-
240
A
V SD
Diode forward voltage
I F = 25 A; V GS = 0 V
-
0.85
1.2
V
I F = 75 A; V GS = 0 V
-
1.1
-
V
t rr
Reverse recovery time
I F = 75 A; -dI F /dt = 100 A/
m
s;
-
400
-
ns
Q rr
Reverse recovery charge
V GS = -10 V; V R = 30 V
-
1.0
-
m
C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
W DSS
Drain-source non-repetitive
I D = 75 A; V DD
£
25 V;
-
-
500
mJ
unclamped inductive turn-off
V GS = 5 V; R GS = 50
W
; T mb = 25 ˚C
energy
August 1999
2
Rev 1.100
22888807.007.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9605-30A
Logic level FET
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1
Zth / (K/W)
D =
0.5
0.1
0.2
0.1
0.05
0.02
P
t p
D =
t p
D
T
0.01
T
t
0
0
20 40 60 80 100 120 140 160 180
Tmb / C
0.001
0.00001
0.001
t/S
0.1
10
Fig.1. Normalised power dissipation.
PD% = 100
×
P D /P D 25 ˚C = f(T mb )
Fig.4. Transient thermal impedance.
Z th j-mb = f(t); parameter D = t p /T
ID%
Normalised Current Derating
400
10.0
7.0
6.0
4.8
120
110
100
90
80
70
60
50
40
30
20
10
0
4.6
VGS/V =
ID/V
4.4
5.0
4.2
300
4.0
3.8
3.6
200
3.4
3.2
3.0
100
2.8
2.6
2.4
0
20 40 60 80 100 120 140 160 180
Tmb / C
0
0
2
4
VDS/V
6
8
10
Fig.2. Normalised continuous drain current.
ID% = 100
I D /I D 25 ˚C = f(T mb ); conditions: V GS
³
5 V
Fig.5. Typical output characteristics, T j = 25 ˚C.
I D = f(V DS ); parameter V GS
1000
11 RDS(ON)/mOhm
ID/A
10
tp =
RDS(ON) = VDS/ID
9
100
100uS
VGS/V =
8
1mS
7
10mS
3.0
3.2
3.4
3.6
4.0
5.0
DC
6
10
100mS
5
4
1
3
1
10
VDS/V
100
0
20
40
ID/A
60
80
100
Fig.3. Safe operating area. T mb = 25 ˚C
I D & I DM = f(V DS ); I DM single pulse; parameter t p
Fig.6. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(I D ); parameter V GS
August 1999
3
Rev 1.100
×
22888807.008.png 22888807.001.png 22888807.002.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9605-30A
Logic level FET
6.5 RDS(ON)/mOhm
2
a
30V TrenchMOS
6
5.5
1.5
5
1
4.5
4
0.5
3.5
-100
0
100
200
3
-50
50
150
3
4
5
6
VGS/V
7
8
9
10
Tj / C
Fig.7. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(V GS ); conditions: I D = 25 A;
Fig.10. Normalised drain-source on-state resistance.
a = R DS(ON) /R DS(ON)25 ˚C = f(T j ); I D = 25 A; V GS = 5 V
100
ID/A
2.5
VGS(TO) / V
BUK959-60
max.
80
2
typ.
60
1.5
Tj/C = 175
25
min.
40
1
20
0.5
0
-100
-50
0
50
100
150
200
0
0.5
1
1.5
2
2.5
3
3.5
VGS/V
Tj / C
Fig.8. Typical transfer characteristics.
I D = f(V GS ) ; conditions: V DS = 25 V; parameter T j
Fig.11. Gate threshold voltage.
V GS(TO) = f(T j ); conditions: I D = 1 mA; V DS = V GS
150
gfs/S
1E-01
Sub-Threshold Conduction
1E-02
100
1E-03
2%
typ
98%
50
1E-04
1E-05
0
0
20
40
ID/A
60
80
100
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.9. Typical transconductance, T j = 25 ˚C.
g fs = f(I D ); conditions: V DS = 25 V
Fig.12. Sub-threshold drain current.
I D = f(V GS) ; conditions: T j = 25 ˚C; V DS = V GS
August 1999
4
Rev 1.100
0
0
22888807.003.png
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9605-30A
Logic level FET
20
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
15
10
Ciss
5
Coss
Crss
0
20
40
60
80
100 120 140 160 180
Tmb / C
0.01
0.1
1
VDS/V
10
100
Fig.13. Typical capacitances, C iss , C oss , C rss .
C = f(V DS ); conditions: V GS = 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
W DSS % = f(T mb ); conditions: I D = 75 A
6
VGS/V
+
VDD
5
L
4
VDS
VDS =
14V
24V
-
3
VGS
-ID/10 0
2
0
T.U.T.
1
RGS
R 01
shunt
0
0
20
40
60
80
100
120
QG/nC
Fig.14. Typical turn-on gate-charge characteristics.
V GS = f(Q G ); conditions: I D = 50 A; parameter V DS
Fig.17. Avalanche energy test circuit.
W DSS =
0.5
×
LI 2
×
BV DSS /(
BV DSS -
V DD )
100
ID/A
+
VDD
80
RD
60
VDS
-
Tj/C =
175
25
VGS
40
RG
0
T.U.T.
20
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
VSDS/V
Fig.15. Typical reverse diode current.
I F = f(V SDS ); conditions: V GS = 0 V; parameter T j
Fig.18. Switching test circuit.
August 1999
5
Rev 1.100
22888807.004.png

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