COMPAL LA-4241P.pdf
(
1167 KB
)
Pobierz
A
B
C
D
E
ZZZ1
ZZZ1
ZZZ3
ZZZ3
ZZZ4
ZZZ4
ZZZ5
ZZZ5
ZZZ6
ZZZ6
PJP1
PJP1
PJP1
PJP1
PCB
14WDAZ@
PCB
14WDAZ@
LA-4241P
14WDA@
LA-4241P
14WDA@
LS-4243P
14WDA@
LS-4243P
14WDA@
LS-4244P
14WDA@
LS-4244P
14WDA@
LS-4249P
14WDA@
LS-4249P
14WDA@
14W_DCIN
14W_45@
14W_DCIN
14W_45@
15W_DCIN
15W_45@
15W_DCIN
15W_45@
1
1
12/21 Add PJP1 for DCIN Cable on 45 Level
One for 14W DCIN , PN: DC301001Y00
Another for 15W DCIN , PN: DC301001V00
ZZZ2
ZZZ2
ZZZ8
ZZZ8
ZZZ9
ZZZ9
ZZZ10
ZZZ10
ZZZ11
ZZZ11
ZZZ12
ZZZ12
ZZZ13
ZZZ13
PCB
15WDAZ@
PCB
15WDAZ@
LA-4241P
15WDA@
LA-4241P
15WDA@
LS-4242P
15WDA@
LS-4242P
15WDA@
LS-4243P
15WDA@
LS-4243P
15WDA@
LS-4244P
15WDA@
LS-4244P
15WDA@
LS-4245P
15WDA@
LS-4245P
15WDA@
LS-4246P
15WDA@
LS-4246P
15WDA@
Compal Confidential
05/20 Add DAZ PCB Panel P/N
JHXXX Schematics Document
2
2
Intel Penryn Processor with Cantiga + DDRII + ICH9M
(With nVIDIA MXM/B)
2008-06-03
REV: 1.0
3
3
4
4
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
2007/08/18
2007/08/18
2007/08/18
2008/8/18
2008/8/18
2008/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Page
Cover Page
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
0.4
0.4
0.4
Date:
Date:
Date:
Tuesday, June 03, 2008
Tuesday, June 03, 2008
Tuesday, June 03, 2008
Sheet
Sheet
Sheet
1
1
1
of
of
of
49
49
49
A
B
C
D
E
A
B
C
D
E
Compal Confidential
Thermal Sensor
Clock Generator
ICS9LPRS387
Intel Penryn Processor
Model Name : JHXXX
Fan Control
page 4
ADT7421
File Name : LA-4241P
uPGA-478 Package
page 4
page 16
page 4,5,6
1
1
FSB
H_A#(3..35)
667/800MHz
H_D#(0..63)
LVDS
LCD Conn.
Memory BUS(DDRII)
page 18
Intel Cantiga
200pin DDRII-SO-DIMM X2
HDMI
Dual Channel
BANK 0, 1, 2, 3
page 14,15
page 25
CRT
page 19
uFCBGA-1329
1.8V DDRII 533/667
PCI-Express
page 7,8,9,10,11,12,13
MXM II VGA/B
DMI
USB conn x3
TO I/O/B
Bluetooth
Conn
CMOS Camera
Finger Print
Conn
X4 mode
page 17
page 35
page 34
page 40
page 40
2
2
PCI-Express
Intel ICH9-M
USB
3.3V 48MHz
3.3V 24.576MHz/48Mhz
HD Audio
BGA-676
S-ATA
page 20,21,22,23
New Card
Socket
MINI Card x3
LAN(GbE)
RTL8111C/8102E
port 0
GMCH HDA
MDC 1.5
Conn
HDA Codec
Card Reader
ALC268
WLAN,
TV-Tuner
Robson
page 8
page 40
page 36
page 31
JMB385
page 30
page 28
page 26
S-ATA HDD
Conn.
S-ATA ODD
Conn.
page 24
page 24
3 in 1
socket
Audio AMP
RJ45
page 37
LPC BUS
page 29
page 26
3
3
RTC CKT.
page 21
ENE KB926
Function/B
page 32
Power USB/B
Power On/Off CKT.
page 33
page 35
Int.KBD
Touch Pad
page 34
USB I/O Conn.
CIR
LID SW
page 33
DC/DC Interface CKT.
BIOS
SCREW
page 41
page 39
page 34
Debug port
Power Circuit DC/DC
page 35
4
4
page 41,42,43,45
46,47,48
TPM
CHARGER
LED
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
page 44
page 40
2007/08/18
2007/08/18
2007/08/18
2008/8/18
2008/8/18
2008/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
0.4
0.4
0.4
Date:
Date:
Date:
Friday, April 11, 2008
Friday, April 11, 2008
Friday, April 11, 2008
Sheet
Sheet
Sheet
2
2
2
of
of
of
49
49
49
A
B
C
D
E
A
B
C
D
E
Voltage Rails
Power Plane
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
1
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
OFF
1
+0.9VS ( Actual +0.9V )
0.9V switched power rail for DDR terminator
ON
ON
+1.05VS
1.05V switched power rail
ON
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+1.8VS
1.8V switched power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
3.3V switched power rail
5V always on power rail
OFF
OFF
ON*
EC SM Bus1 address
EC SM Bus2 address
+5VALW
ON
ON
+5VS
5V switched power rail
ON
OFF
OFF
Device
Address
Device
Address
1001 100X b
+VSB
VSB always on power rail
ON
ON
ON*
Smart Battery
0001 011X b
ADI ADM1032
+RTCVCC
RTC power
ON
ON
ON
EEPROM(24C16/02)
1010 000X b
NVIDIA NB8X
ICH9M SM Bus address
2
2
Device
Address
SIGNAL
STATE
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
+VALW
+V
+VS
Clock
Clock Generator
(ICS9LPRS325AKLFT_MLF72)
1101 001Xb
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
DDR DIMM0
1010 000Xb
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
DDR DIMM1
1010 010Xb
R472
R472
R472
R472
R472
R472
R472
R472
R472
R472
S3 (Suspend to RAM)
LOW
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
SKU ID Table
4.7K_0402_5%
H_14_C@
4.7K_0402_5%
H_14_C@
10K_0402_5%
H_14_MP@
10K_0402_5%
H_14_MP@
18K_0402_5%
H_15_B@
18K_0402_5%
H_15_B@
27K_0402_5%
H_15_C@
27K_0402_5%
H_15_C@
39K_0402_5%
H_15_MP@
39K_0402_5%
H_15_MP@
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Vcc
3.3V +/- 5%
47K +/- 5%
Rb
R472
R472
R472
R472
R472
R472
R472
R472
R472
R472
Rb~ R470
Ra~ R472
PROJECT ID Table
56K_0402_5%
L_14_B@
56K_0402_5%
L_14_B@
82K_0402_5%
L_14_C@
82K_0402_5%
L_14_C@
120K_0402_5%
L_14_MP@
120K_0402_5%
L_14_MP@
220K_0402_5%
L_15_B@
220K_0402_5%
L_15_B@
470K_0402_5%
L_15_C@
470K_0402_5%
L_15_C@
ID1
ID0
R357
R355
Board ID
Rb
Ra
V
min
V
typ
V
AD_BID
max
Ra BOM Structure
AD_BID
AD_BID
3
3
JHT00 ( 00@ )
R361
1
NA
4.7K +/- 5%
0 V
0.274 V
0 V
0 V
H_14_B@
H_14_C@
H_14_MP@
H_15_B@
H_15_C@
H_15_MP@
L_14_B@
L_14_C@
L_14_MP@
L_15_B@
L_15_C@
NA for L_15_MP
JHT01 ( 01@ )
R361
2
47K(RB@)
4.7K +/- 5%
0.300 V
0.328 V
JHL90 ( 10@ )
R360
R357
3
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
10K +/- 5%
18K +/- 5%
27K +/- 5%
39K +/- 5%
56K +/- 5%
0.553V
0.849V
0.578 V
0.913V
0.628 V
0.981 V
JHL91 ( 11@ )
R360
R355
4
5
1.129 V
1.415 V
1.204 V
1.282 V
6
1.496 V
1.579 V
7
1.712 V
2.020V
1.794 V
2.097 V
1.876 V
MIC ID Table
8
82K +/- 5%
120K +/- 5%
220K +/- 5%
470K +/- 5%
NA
2.173 V
9
2.303 V
2.670 V
2.972 V
3.135 V
2.371 V
2.719 V
3.000 V
3.300 V
2.437 V
2.765 V
3.026 V
3.465 V
R
Structure
10
R585 Single MIC
SINGLE@
11
R583 Array MIC
DUAL@
12
4
4
Compal Secret Data
Compal Secret Data
Compal Secret Data
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
2007/08/18
2007/08/18
2007/08/18
2008/8/18
2008/8/18
2008/8/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
0.4
0.4
0.4
Date:
Date:
Date:
Tuesday, June 03, 2008
Tuesday, June 03, 2008
Tuesday, June 03, 2008
Sheet
Sheet
Sheet
3
3
3
of
of
of
49
49
49
A
B
C
D
E
5
4
3
2
1
+1.05VS
EMI Recommend
Which to follow?
H_IERR#
R12
R12
56_0402_5%
56_0402_5%
Checklist
CRB
1
2
D
D
TCK
TDI
TMS
TRST#
PREQ#
55_5%
55_5%
55_1%
55_5%
x
54.9_1%
ITP_TMS
R13
R13
1
2
54.9_0402_1%
54.9_0402_1%
H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]
54.9_1%
54.9_1%
54.9_1%
54.9_1%
ITP_TDI
R14
R14
1
2
54.9_0402_1%
54.9_0402_1%
<7>
H_A#[3..35]
H_PROCHOT#
R15
R15
56_0402_5%
56_0402_5%
1
2
<7>
H_REQ#[0..4]
ITP_TCK
ITP_TRST#
R16
R16
54.9_0402_1%
54.9_0402_1%
1
2
<7>
H_RS#[0..2]
JCPU1A
JCPU1A
R17
R17
54.9_0402_1%
54.9_0402_1%
1
2
H_A#3
J4
H1
A[3]#
ADS#
H_ADS#
<7>
H_A#4
L5
E2
A[4]#
BNR#
H_BNR#
<7>
H_A#5
L4
G5
A[5]#
BPRI#
H_BPRI# <7>
H_DEFER#
H_A#6
K5
A[6]#
H_A#7
H_A#9
H_A#10
H_A#12
M3
H5
A[7]#
DEFER#
<7>
H_A#8
N2
F21
A[8]#
DRDY#
H_DRDY#
<7>
1/29 change to EMC1402 pn
J1
E1
A[9]#
DBSY#
H_DBSY#
<7>
EMC1402
N3
A[10]#
H_A#11
U1
U1
P5
F1
A[11]#
BR0#
H_BR0#
<7>
+3VS
P2
A[12]#
H_A#13
H_IERR#
C1
0.1U_0402_16V4Z
1
C1
0.1U_0402_16V4Z
L2
D20
A[13]#
IERR#
H_A#14
P4
B3
A[14]#
INIT#
H_INIT#
<21>
H_A#15
P1
2
A[15]#
H_A#16
R1
H4
A[16]#
LOCK#
H_LOCK#
<7>
LM95245CIMMX NOPB MSOP 8P
NS@
LM95245CIMMX NOPB MSOP 8P
NS@
M1
<7>
H_ADSTB#0
ADSTB[0]#
C1
H_RESET#
RESET#
H_RESET#
<7>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#4
K3
F3
H_RS#0
H_RS#2
REQ[0]#
RS[0]#
H2
F4
H_RS#1
U1
U1
1
REQ[1]#
RS[1]#
K2
G3
C2
2200P_0402_50V7K
1
8
EC_SMB_CK2
<17,32>
REQ[2]#
RS[2]#
VDD
SCLK
C
H_REQ#3
C
J3
G2
H_TRDY#
<7>
REQ[3]#
TRDY#
THERMDA
L1
2
7
REQ[4]#
2
D+
SDATA
EC_SMB_DA2
<17,32>
G6
HIT#
H_HIT#
<7>
H_A#17
THERMDC
Y2
E4
3
6
2
1
+3VS
A[17]#
HITM#
H_HITM#
<7>
D-
ALERT/THERM2
H_A#18
H_A#19
H_A#20
H_A#22
R19
R19
R20
R20
R706
R706
10K_0402_5%
10K_0402_5%
U5
A[18]#
R3
AD4
1
2
4
5
+3VS
A[19]#
BPM[0]#
THERM
GND
R18
R18
10K_0402_5%
10K_0402_5%
W6
AD3
A[20]#
BPM[1]#
H_A#21
H_A#23
H_A#24
H_A#26
U4
AD1
A[21]#
BPM[2]#
ADT7421ARMZ-REEL_MSOP8
SMSC@
ADT7421ARMZ-REEL_MSOP8
SMSC@
Y5
AC4
A[22]#
BPM[3]#
EMI Recommend
Address:100_1100
U1
AC2
A[23]#
PRDY#
0_0402_5%
NS@
0_0402_5%
NS@
0_0402_5%
NS@
0_0402_5%
NS@
R4
AC1
A[24]#
PREQ#
H_A#25
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
ITP_TCK
T5
AC5
A[25]#
TCK
ITP_TDI
ITP_TMS
T3
AA6
A[26]#
TDI
W2
AB3
A[27]#
TDO
W5
AB5
A[28]#
TMS
ITP_TRST#
Y4
AB6
A[29]#
TRST#
ITP_DBRESET#
U2
C20
FAN1 Conn
A[30]#
DBR#
ITP_DBRESET#
<22>
V4
A[31]#
H_A#32
H_A#33
H_A#34
H_A#35
W3
A[32]#
H_PROCHOT#
<48>
AA4
THERMAL
THERMAL
A[33]#
AB2
A[34]#
AA3
D21
H_PROCHOT#
A[35]#
PROCHOT#
V1
A24
THERMDA_R
THERMDC_R
R19
R19
SMSC@
SMSC@
100_0402_5%
100_0402_5%
THERMDA
THERMDC
ADSTB[1]#
THERMDA
<7>
H_ADSTB#1
B25
R20
R20
SMSC@
SMSC@
100_0402_5%
100_0402_5%
THERMDC
+5VS
A6
<21>
H_A20M#
A20M#
+5VS
C3
C3
10U_0805_10V4Z
10U_0805_10V4Z
A5
C7
1
2
<21>
H_FERR#
H_THERMTRIP#
<8,21>
FERR#
THERMTRIP#
R705
R705
0_0402_5%
0_0402_5%
C4
1
2
<21>
H_IGNNE#
IGNNE#
D5
<21>
H_STPCLK#
STPCLK#
B
B
H CLK
H CLK
U2
U2
D1
BAS16_SOT23-3
C6
<21>
H_INTR
LINT0
B4
A22
1
8
<21>
H_NMI
CLK_CPU_BCLK
<16>
LINT1
BCLK[0]
VEN
GND
A3
A21
2
7
<21>
H_SMI#
CLK_CPU_BCLK#
<16>
SMI#
BCLK[1]
VIN
GND
+VCC_FAN1
3
6
VO
GND
R
815
330_0402_5%
EN_FAN1_R
D2
D2
M4
1
2
4
5
RSVD[01]
<32>
EN_FAN1
VSET
GND
N5
1
2
RSVD[02]
C769
0.047U_0402_16V7K
G990P11U_SOP8
G990P11U_SOP8
T2
RSVD[03]
BAS16_SOT23-3
BAS16_SOT23-3
V3
RSVD[04]
Layout Note:
THERMDA&THERMDC Trace / Space = 10 / 10 mil
B2
RSVD[05]
C4
C4
10U_0805_10V4Z
10U_0805_10V4Z
C3
RSVD[06]
D2
1
2
RSVD[07]
THERMDA_R&THERMDC_R Trace / Space = 10 / 10 mil
D22
RSVD[08]
+3VS
C5
1000P_0402_50V7K
C5
1000P_0402_50V7K
1
D3
RSVD[09]
F6
RSVD[10]
2
R21
10K_0402_5%
Merom Ball-out Rev 1a
CONN@
Merom Ball-out Rev 1a
CONN@
40mil
JP7
JP7
+VCC_FAN1
1
1
2
<32>
FAN_SPEED1
2
3
3
1
C6
1000P_0402_50V7K
4
GND
5
GND
2
ACES_85205-03001
ACES_85205-03001
A
A
CONN@
CONN@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2007/08/18
2007/08/18
2007/08/18
2008/08/18
2008/08/18
2008/08/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Penryn (1/3)
Penryn (1/3)
Penryn (1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
0.4
0.4
0.4
Date:
Date:
Date:
Tuesday, June 03, 2008
Tuesday, June 03, 2008
Tuesday, June 03, 2008
Sheet
Sheet
Sheet
4
4
4
of
of
of
49
49
49
5
4
3
2
1
5
4
3
2
1
H_D#[0..63]
JCPU1C
JCPU1C
H_D#[0..63]
<7>
A7
AB20
+CPU_CORE
+CPU_CORE
VCC[001]
VCC[068]
JCPU1B
JCPU1B
A9
AB7
VCC[002]
VCC[069]
H_D#0
H_D#32
H_D#34
H_D#35
H_D#37
H_D#39
E22
Y22
A10
AC7
D[0]#
D[32]#
VCC[003]
VCC[070]
H_D#1
H_D#3
F24
AB24
H_D#33
A12
AC9
D
D
D[1]#
D[33]#
VCC[004]
VCC[071]
H_D#2
E26
V24
A13
AC12
D[2]#
D[34]#
VCC[005]
VCC[072]
G22
V26
A15
AC13
D[3]#
D[35]#
VCC[006]
VCC[073]
H_D#4
F23
V23
H_D#36
A17
AC15
D[4]#
D[36]#
VCC[007]
VCC[074]
H_D#5
H_D#6
G25
T22
A18
AC17
D[5]#
D[37]#
VCC[008]
VCC[075]
H_D#38
E25
U25
A20
AC18
D[6]#
D[38]#
VCC[009]
VCC[076]
H_D#7
E23
U23
B7
AD7
D[7]#
D[39]#
VCC[010]
VCC[077]
H_D#8
H_D#10
H_D#11
H_D#40
K24
Y25
B9
AD9
D[8]#
D[40]#
VCC[011]
VCC[078]
H_D#9
H_D#41
G24
W22
B10
AD10
D[9]#
D[41]#
VCC[012]
VCC[079]
H_D#42
J24
Y23
B12
AD12
D[10]#
D[42]#
VCC[013]
VCC[080]
H_D#43
J23
W24
B14
AD14
D[11]#
D[43]#
VCC[014]
VCC[081]
H_D#12
H_D#14
H_D#44
H22
W25
B15
AD15
D[12]#
D[44]#
VCC[015]
VCC[082]
H_D#13
H_D#45
H_D#46
H_D#47
F26
AA23
B17
AD17
D[13]#
D[45]#
VCC[016]
VCC[083]
K22
AA24
B18
AD18
D[14]#
D[46]#
VCC[017]
VCC[084]
H_D#15
H23
AB25
B20
AE9
D[15]#
D[47]#
VCC[018]
VCC[085]
J26
Y26
C9
AE10
<7>
H_DSTBN#0
DSTBN[0]#
DSTBN[2]#
H_DSTBN#2
<7>
VCC[019]
VCC[086]
H26
AA26
C10
AE12
<7>
H_DSTBP#0
DSTBP[0]#
DSTBP[2]#
H_DSTBP#2
<7>
VCC[020]
VCC[087]
H25
U22
C12
AE13
<7>
H_DINV#0
DINV[0]#
DINV[2]#
H_DINV#2
<7>
VCC[021]
VCC[088]
C13
AE15
VCC[022]
VCC[089]
C15
AE17
VCC[023]
VCC[090]
H_D#16
H_D#17
H_D#19
H_D#48
N22
AE24
C17
AE18
D[16]#
D[48]#
VCC[024]
VCC[091]
H_D#49
H_D#50
K25
AD24
C18
AE20
D[17]#
D[49]#
VCC[025]
VCC[092]
H_D#18
P26
AA21
D9
AF9
D[18]#
D[50]#
VCC[026]
VCC[093]
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
R23
AB22
D10
AF10
330u
ESR 9m ohm
Package(L*W*H)7.3*4.3*1.8
Rating 2.5V
D[19]#
D[51]#
VCC[027]
VCC[094]
H_D#20
L23
AB21
D12
AF12
D[20]#
D[52]#
VCC[028]
VCC[095]
H_D#21
M24
AC26
D14
AF14
D[21]#
D[53]#
VCC[029]
VCC[096]
H_D#22
L22
AD20
D15
AF15
D[22]#
D[54]#
VCC[030]
VCC[097]
H_D#23
M23
AE22
D17
AF17
D[23]#
D[55]#
VCC[031]
VCC[098]
H_D#24
H_D#25
P25
AF23
H_D#56
H_D#57
H_D#59
D18
AF18
D[24]#
D[56]#
VCC[032]
VCC[099]
C
C
P23
AC25
E7
AF20
D[25]#
D[57]#
VCC[033]
VCC[100]
+1.05VS
H_D#26
H_D#28
H_D#58
H_D#60
H_D#62
P22
AE21
E9
D[26]#
D[58]#
VCC[034]
H_D#27
T24
AD21
E10
G21
+1.05VS
D[27]#
D[59]#
VCC[035]
VCCP[01]
R24
AC22
E12
V6
D[28]#
D[60]#
VCC[036]
VCCP[02]
H_D#29
H_D#61
H_D#63
L25
AD23
E13
J6
1
D[29]#
D[61]#
VCC[037]
VCCP[03]
H_D#30
H_D#31
T25
AF22
E15
K6
D[30]#
D[62]#
VCC[038]
VCCP[04]
R22
1K_0402_1%
+
C7
330U_D2E_2.5VM_R9
N25
AC23
E17
M6
D[31]#
D[63]#
VCC[039]
VCCP[05]
L26
AE25
E18
J21
<7>
H_DSTBN#1
H_DSTBN#3
<7>
DSTBN[1]#
DSTBN[3]#
VCC[040]
VCCP[06]
M26
AF24
E20
K21
<7>
H_DSTBP#1
DSTBP[1]#
DSTBP[3]#
H_DSTBP#3
<7>
VCC[041]
VCCP[07]
2
N24
AC20
F7
M21
<7>
H_DINV#1
DINV[1]#
DINV[3]#
H_DINV#3
<7>
VCC[042]
VCCP[08]
Trace Close CPU < 0.5'
F9
N21
VCC[043]
VCCP[09]
GTL_REF0
TEST1
TEST2
TEST4
COMP0
R23
R23
27.4_0402_1%
27.4_0402_1%
AD26
R26
1
2
F10
N6
GTLREF
COMP[0]
VCC[044]
VCCP[10]
R24
R24
@
@
1K_0402_5%
1K_0402_5%
MISC
MISC
COMP1
R25
R25
54.9_0402_1%
54.9_0402_1%
2
1
C23
U26
1
2
F12
R21
TEST1
COMP[1]
VCC[045]
VCCP[11]
R26
R26
@
@
1K_0402_5%
1K_0402_5%
COMP2
R27
R27
27.4_0402_1%
27.4_0402_1%
2
1
D25
AA1
1
2
F14
R6
TEST2
COMP[2]
VCC[046]
VCCP[12]
Width=4 mil ,
Spacing: 15mil
(55Ohm)
@
@
TEST3
TEST5
TEST6
COMP3
R29
R29
54.9_0402_1%
54.9_0402_1%
C24
Y1
1
2
F15
T21
T1
T1
PAD
PAD
TEST3
COMP[3]
VCC[047]
VCCP[13]
R28
2K_0402_1%
C8
0.1U_0402_16V4Z
C8
0.1U_0402_16V4Z
1
2
AF26
F17
T6
TEST4
VCC[048]
VCCP[14]
@
@
@
@
AF1
E5
F18
V21
PAD
PAD
T2
T2
TEST5
DPRSTP#
H_DPRSTP#
<8,21,48>
VCC[049]
VCCP[15]
@
@
A26
B5
F20
W21
PAD
PAD
T3
T3
TEST6
DPSLP#
H_DPSLP#
<21>
VCC[050]
VCCP[16]
D24
AA7
20mils
DPWR#
H_DPWR#
<7>
VCC[051]
H_PWRGOOD
H_CPUSLP#
B22
D6
AA9
B26
+1.5VS
<16>
CPU_BSEL0
BSEL[0]
PWRGOOD
H_PWRGOOD
<21>
VCC[052]
VCCA[01]
B23
D7
AA10
C26
<16>
CPU_BSEL1
BSEL[1]
SLP#
H_CPUSLP#
<7>
VCC[053]
VCCA[02]
C21
AE6
AA12
1
1
<16>
CPU_BSEL2
BSEL[2]
PSI#
H_PSI#
<48>
VCC[054]
AA13
AD6
C9
C9
C10
10U_0805_10V4Z
VCC[055]
VID[0]
CPU_VID0
<48>
Merom Ball-out Rev 1a
CONN@
Merom Ball-out Rev 1a
CONN@
AA15
AF5
CPU_VID1
<48>
VCC[056]
VID[1]
AA17
AE5
CPU_VID2
<48>
VCC[057]
VID[2]
2
2
TRACE CLOSELY CPU < 0.5'
AA18
AF4
CPU_VID3
<48>
VCC[058]
VID[3]
0.01U_0402_16V7K
0.01U_0402_16V7K
AA20
AE3
CPU_VID4
<48>
VCC[059]
VID[4]
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)
AB9
AF3
CPU_VID5
<48>
VCC[060]
VID[5]
AC10
AE2
CPU_VID6
<48>
VCC[061]
VID[6]
B
B
AB10
1
2
+CPU_CORE
VCC[062]
R30
R30
100_0402_1%
100_0402_1%
AB12
VCC[063]
VCCSENSE
AB14
AF7
VCCSENSE
<48>
VCC[064]
VCCSENSE
AB15
VCC[065]
AB17
VCC[066]
VSSSENSE
AB18
AE7
VCC[067]
VSSSENSE
VSSSENSE
<48>
H_PSI#
H_DPRSTP#
C739
C739
@
@
100P_0402_50V8J
100P_0402_50V8J
1
2
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
1
2
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CONN@
CONN@
R31
R31
100_0402_1%
100_0402_1%
1
2
.
.
C762
C762
470P_0402_50V7K
470P_0402_50V7K
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
0
1
1
Place PU and PD within 1 inch of CPU (CRB recommend)
Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mils spacing.
200
0
1
0
For 6 layer
Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.
266
0
0
0
Length matching within 25 mils (Compal Common Design)
Trace width/space/other is 20/7/25
Place these 2 resisters closk to CPU pins within 500 mils
A
A
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2007/08/18
2007/08/18
2007/08/18
2008/08/18
2008/08/18
2008/08/18
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Penryn (2/3)
Penryn (2/3)
Penryn (2/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
B
B
B
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
JHXXX M/B LA-4241P Schematic
0.4
0.4
0.4
Date:
Date:
Date:
Wednesday, May 28, 2008
Wednesday, May 28, 2008
Wednesday, May 28, 2008
Sheet
Sheet
Sheet
5
5
5
of
of
of
49
49
49
5
4
3
2
1
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