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Philips Semiconductors
Product specification
Logic level TrenchMOS TM transistor
IRLZ34N
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope using ’ trench ’
DS
Drain-source voltage
55
V
technology. The device features very
I D
Drain current (DC)
30
A
low on-state resistance and has
P tot
Total power dissipation
68
W
integral zener diodes giving ESD
T j
Junction temperature
175
˚C
protection up to 2kV. It is intended for
R DS(ON)
Drain-source on-state
35
m
W
use in switched mode power supplies
resistance
V GS = 10 V
and general purpose switching
applications.
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
d
tab
1
gate
2
drain
3
source
g
tab drain
123
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V DSS
Drain-source voltage
T j = 25 ˚C to 175˚C
-
55
V
V DGR
Drain-gate voltage
T j = 25 ˚C to 175˚C; R GS = 20 k
W
-
55
V
V GS
Gate-source voltage
-
±
13
V
I D
Continuous drain current
T mb = 25 ˚C
-
30
A
T mb = 100 ˚C
-
21
A
I DM
Pulsed drain current
T mb = 25 ˚C
-
110
A
P D
Total power dissipation
T mb = 25 ˚C
-
68
W
T j , T stg
Operating junction and
- 55
175
˚C
storage temperature
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R th j-mb
Thermal resistance junction
-
2.2
K/W
to mounting base
R th j-a
Thermal resistance junction
60
-
K/W
to ambient
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V C
Electrostatic discharge
Human body model (100 pF, 1.5 k
W
)
-
2
kV
capacitor voltage, all pins
February 1999
1
Rev 1.000
N-channel enhancement mode
22890164.002.png
Philips Semiconductors
Product specification
Logic level TrenchMOS TM transistor
IRLZ34N
ELECTRICAL CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V (BR)DSS
Drain-source breakdown
V GS = 0 V; I D = 0.25 mA;
55
-
-
V
voltage
T j = -55˚C
50
-
-
V
V (BR)GSS
Gate-source breakdown
I G =
±
1 mA;
10
-
-
V
voltage
V GS(TO)
Gate threshold voltage
V DS = V GS ; I D = 1 mA
1.0
1.5
2.0
V
T j = 175˚C
0.5
-
-
V
T j = -55˚C
-
-
2.3
V
R DS(ON)
Drain-source on-state
V GS = 5 V; I D = 17 A
-
28
46
m
W
resistance
V GS = 10 V; I D = 17 A
-
26
35
m
W
T j = 175˚C
-
-
74
m
W
g fs
Forward transconductance
V DS = 25 V; I D = 15 A
12
40
-
S
I GSS
Gate source leakage current V GS =
±
5 V; V DS = 0 V
-
0.02
1
m
A
T j = 175˚C
-
-
20
m
A
I DSS
Zero gate voltage drain
V DS = 55 V; V GS = 0 V;
-
0.05
10
m
A
current
T j = 175˚C
-
-
500
m
A
Q g(tot)
Total gate charge
I D = 30 A; V DD = 44 V; V GS = 5 V
-
22.5
-
nC
Q gs
Gate-source charge
-
6
-
nC
Q gd
Gate-drain (Miller) charge
-
11
-
nC
t d on
Turn-on delay time
V DD = 30 V; I D = 25 A;
-
14
21
ns
t r
Turn-on rise time
V GS = 5 V; R G = 10
W
-
77
110
ns
t d off
Turn-off delay time
Resistive load
-
55
80
ns
t f
Turn-off fall time
-
48
65
ns
L d
Internal drain inductance
Measured from tab to centre of die
-
3.5
-
nH
L d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C iss
Input capacitance
V GS = 0 V; V DS = 25 V; f = 1 MHz
-
1050 1400 pF
C oss
Output capacitance
-
205 245
pF
C rss
Feedback capacitance
-
113 150
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I S
Continuous source current
-
-
30
A
(body diode)
I SM
Pulsed source current (body
-
-
110
A
diode)
V SD
Diode forward voltage
I F = 25 A; V GS = 0 V
-
0.95 1.2
V
I F = 34 A; V GS = 0 V
-
1.0
-
V
t rr
Reverse recovery time
I F = 34 A; -dI F /dt = 100 A/
m
s;
-
40
-
ns
Q rr
Reverse recovery charge
V GS = -10 V; V R = 30 V
-
0.16
-
m
C
February 1999
2
Rev 1.000
N-channel enhancement mode
22890164.003.png
Philips Semiconductors
Product specification
Logic level TrenchMOS TM transistor
IRLZ34N
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W DSS
Drain-source non-repetitive I D = 20 A; V DD
£
25 V; V GS = 5 V;
-
45
mJ
unclamped inductive turn-off R GS = 50
W
; T mb = 25 ˚C
energy
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID/A
100
RDS(ON) = VDS/ID
tp =
1 us
10us
DC
100 us
10
1 ms
10ms
100ms
0
20 40 60 80 100 120 140 160 180
Tmb / C
1
1
10
100
VDS/V
Fig.1. Normalised power dissipation.
PD% = 100
×
P D /P D 25 ˚C = f(T mb )
Fig.3. Safe operating area. T mb = 25 ˚C
I D & I DM = f(V DS ); I DM single pulse; parameter t p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
10 ZTH/ (K/W)
1
0.5
0.2
0.1
0.05
0.02
P
t p
D =
t p
D
T
0.1
T
t
0
0.01
0
20 40 60 80 100 120 140 160 180
Tmb / C
1.0E-06
0.0001
0.01
1
100
t/s
Fig.2. Normalised continuous drain current.
ID% = 100
I D /I D 25 ˚C = f(T mb ); conditions: V GS
³
5 V
Fig.4. Transient thermal impedance.
Z th j-mb = f(t); parameter D = t p /T
February 1999
3
Rev 1.000
N-channel enhancement mode
×
22890164.004.png
Philips Semiconductors
Product specification
Logic level TrenchMOS TM transistor
IRLZ34N
Drain current, ID (A)
Transconductance, gfs (S)
30
100
10
VGS = 6.0 V
5.6
7
25
80
5.0
60
4.6
20
40
4.0
15
3.6
20
3.0
10
0
0
2
4
6
8
10
5
0
10
20
30
40
50
60
70
Drain-source voltage, VDS (V)
Drain current, ID (A)
Fig.5. Typical output characteristics, T j = 25 ˚C.
I D = f(V DS ); parameter V GS
Fig.8. Typical transconductance, T j = 25 ˚C.
g fs = f(I D ); conditions: V DS = 25 V
45 RDS(ON)/mOhm
2.5
a
BUK959-60
Rds(on) normlised to 25degC
VGS/V =
4
40
4.2
2
4.4
35
4.6
1.5
4.8
5
30
1
0.5
25
0
10
20
30
ID/A
40
50
60
-100
-50
0
Tmb / degC
50
100
150
200
Fig.6. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(I D ); parameter V GS
Fig.9. Normalised drain-source on-state resistance.
a = R DS(ON) /R DS(ON)25 ˚C = f(T j ); I D = 17 A; V GS = 5 V
70
ID/A
2.5
VGS(TO) / V
BUK959-60
60
max.
2
50
typ.
40
1.5
min.
30
1
20
0.5
10
Tj/C = 175
25
0
0
-100
-50
0
50
100
150
200
0
1
2
3
4
5
6
7
VGS/V
Tj / C
Fig.7. Typical transfer characteristics.
I D = f(V GS ) ; conditions: V DS = 25 V; parameter T j
Fig.10. Gate threshold voltage.
V GS(TO) = f(T j ); conditions: I D = 1 mA; V DS = V GS
February 1999
4
Rev 1.000
N-channel enhancement mode
22890164.005.png
Philips Semiconductors
Product specification
Logic level TrenchMOS TM transistor
IRLZ34N
1E-01
Sub-Threshold Conduction
100
IF/A
1E-02
80
1E-03
2%
typ
98%
60
Tj/C = 175
25
1E-04
40
1E-05
20
1E-05
0
0
0.5
1
1.5
0
0.5
1
1.5
2
2.5
3
VSDS/V
Fig.11. Sub-threshold drain current.
I D = f(V GS) ; conditions: T j = 25 ˚C; V DS = V GS
Fig.14. Typical reverse diode current.
I F = f(V SDS ); conditions: V GS = 0 V; parameter T j
2.5
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
2.0
1.5
1.0
Ciss
0.5
0
Coss
Crss
20
40
60
80
100 120 140 160 180
Tmb / C
0.01
0.1
1
VDS/V
10
100
Fig.12. Typical capacitances, C iss , C oss , C rss .
C = f(V DS ); conditions: V GS = 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
W DSS % = f(T mb ); conditions: I D = 20 A
6
VGS/V
+
VDD
5
L
VDS = 14V
4
VDS
VDS = 44V
-
VGS
3
-ID/10 0
2
0
T.U.T.
RGS
R 01
1
shunt
0
0
5
10
15
20
25
QG/nC
Fig.16. Avalanche energy test circuit.
Fig.13. Typical turn-on gate-charge characteristics.
V GS = f(Q G ); conditions: I D = 30 A; parameter V DS
W DSS =
0.5
×
LI 2
×
BV DSS /(
BV DSS -
V DD )
February 1999
5
Rev 1.000
N-channel enhancement mode
22890164.001.png

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