X650 SVC Manual.pdf

GSM TELEPHONE

SGH-X650

GSM TELEPHONE

CONTENTS

1. Specification

2. Circuit Description

3. Exploded Views and Parts List

4. Electrical Parts List

5. Block Diagrams

6. PCB Diagrams

7. Flow Chart of Troubleshooting

8. Disassembly and

Assembly instructions

1. Specification

1-1. GSM General Specification

GSM900

Phase 1

DCS1800

Phase 1

PC1900

Phase 1

Freq. Band[MHz]

Uplink/Downlink

890~915

935~960

1710~1785

1805~1880

1850~1910

1930~1990

ARFCN range

1~124

512~885

512~810

Tx/Rx spacing

45MHz

95MHz

80MHz

Mod. Bit rate/

Bit Period

270.833kbps

3.692us

270.833kbps

3.692us

270.833kbps

3.692us

Time Slot

Period/Frame Period

576.9us

4.615ms

576.9us

4.615ms

576.9us

4.615ms

Modulation

0.3GMSK

MS Power

33dBm~5dBm

30dBm~0dBm

Power Class

5pcl ~ 19pcl

0pcl ~ 15pcl

Sensitivity

-102dBm

-100dBm

TDMA Mux

Cell Radius

35Km

2Km

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Specification

1-2. GSM TX power class

TX Power

control level

GSM900

TX Power

control level

DCS1800

TX Power

control level

PCS1900

33±2 dBm

30±3 dBm

31±2 dBm

28±3 dBm

29±2 dBm

26±3 dBm

27±2 dBm

24±3 dBm

25±2 dBm

22±3 dBm

23±2 dBm

20±3 dBm

21±2 dBm

18±3 dBm

19±2 dBm

16±3 dBm

17±2 dBm

14±3 dBm

15±2 dBm

12±4 dBm

13±2 dBm

10±4 dBm

11±3 dBm

8±4dBm

9±3dBm

6±4 dBm

7±3 dBm

4±4 dBm

5±3 dBm

2±5 dBm

0±5 dBm

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2. Circuit Description

2-1. SGH-X650 RF Circuit Description

2-1-1. RX PART

- FEM(U201) → Switching Tx, Rx path for GSM900, DCS1800, PCS1900 by logic controlling.

- FEM Control Logic (U201) → Truth Table

VC1

VC2

VC3

Tx Mode (GSM900)

Tx Mode (DCS1800/1900)

Rx Mode (GSM900)

Rx Mode (DCS1800)

Rx Mode (PCS1900)

- VC-TCXO (OSC101)

This module generates the 26MHz reference clock to drive the logic and RF. After division by two a reference clock of

13MHz is supplied to the other parts of the system through the pin CLKOUT. After additional process, the reference

clock applies to the U100 Rx IQ demodulator and Tx IQ modulator. And then, the oscillator is controlled by serial data

to select channel and use fast lock mode for GPRS high class operation.

- Transceiver (U100)

The receiver front-end which amplifies the GSM, DCS aerial signal, converts the chosen channel down to a low IF signal

of 100 kHz. The first stages are symmetrical low noise amplifiers (LNAs). The LNAs are followed by an IQ down mixer.

It consists of two mixers in parallel but driven by quadrature out of phase LO signals. The In phase (I) and Quadrature

phase (Q) IF signals are low pass filtered to provide protection from high frequency offset interferes. The low IF I and Q

signals are then fed into the channel filter. The front-end low IF I and Q outputs enter the integrated bandpass channel

filter with provision for five 8 dB gain steps in front of the filter.

2-1-2. TX PART

I and Q baseband signals are applied to the IQ modulator that shifts the modulation spectrum up to the transmit IF. It is

designed for low harmonic distortion, low carrier leakage and high image rejection to keep the phase error as small as

possible.

The modulator is loaded at its IF output by an integrated low pass filter that suppress unwanted spurs prior to get into

the phase detector. The clock drive is generated by division of the RFLO signal provided for the transmit offset mixer.

Baseband IQ signal fed into offset PLL, this function is included inside of U101 chip. OSC100 chip generates modulator

signal which power level is about 6.5dBm and fed into Power Amplifier(U200). The PA output power and power ramping

are well controlled by Auto Power Control circuit. We use offset PLL below table.

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Circuit Description

200kHz offset

30 kHz bandwidth

GSM

-35dBc

DCS

-35dBc

Modulation Spectrum

400kHz offset

30 kHz bandwidth

GSM

-66dBc

DCS

-65dBc

600kHz ~ 1.8MHz offset

30 kHz bandwidth

GSM

-75dBc

DCS

-68dBc

2-2. Baseband Circuit description of SGH-X650

2-2-1. PCF50601

- Power Management

Ten low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system

performance and long battery life. A programmable boost converter provides support for 1.8V, 3.0VSIMs, while a self-

resetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as RTC

module and High Voltage Charge pump, Clock generator, aid in reducing both board area and system complexity.

I2C BUS serial interface provides access to control and configuration registers. This interface gives a microprocessor full

control of the PCF50601 and enables system designers to maximize both standby and talk times.

Supervisory functions. including a reset generator, an input voltage monitor, and a temperature sensor, support reliable

system design. These functions work together to ensure proper system behavior during start-up or in the event of a fault

condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature).

-Backlight Brightness Modulator

The Backlight Brightness Modulator (BBM) contains a programmable Pulse-width modulator (PWM) and FET

to modulate the intensity of a series of LED's or to control a DC/DC converter that drives LCD backlight.

This phone (SGH-X650) use PWM control to contrast the backlight brightness.

- Clock Generato r

The Clock Generator (CG) generates all clocks for internal and external usage. The 32768 Hz crystal

oscillator provides an accurate low clock frequency for the PCF50601 and other circuitry.

2-2-2. LCD Connector

LCD is consisted of main LCD(color 65K UFB LCD).

Chip select signals LCD_MAIN_CS can enable main LCD. BACKLIGHT signal enables white LED of main LCD.

"LCD_RESET" signal initiates the reset process of the LCD.

16-bit data lines(HD(0)~HD(15)) transfers data and commands to LCD. Data and commands use "HA(1)" signal. If this

signal is low, inputs to LCD are commands. If it is high, inputs to LCD are data.

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