EMIF10-LCD02F3.pdf

EMIF10-LCD02F3

10-line IPAD™, EMI filter and ESD protection for LCD and cameras

Features

■

Lead-free package

■

EMI symmetrical (I/O) low-pass filter

■

High efficiency in EMI filtering

■

400 µm pitch

■

Compatible with high speed data rate

Flip Chip

24 bumps

■

Very low PCB space occupation: < 4mm 2

■

Very thin package: 0.60 mm

■

High efficiency in ESD suppression

Figure 1. Pin layout (bump side)

High reliability offered by monolithic integration

■

High reduction of parasitic elements through

integration and wafer level packaging

GND

Complies with the following standards

IEC61000-4-2 level 4 on inputs and outputs

– 15 kV (air discharge)

– 8 kV (contact discharge)

■

GND

MIL STD 883E - Method 3015-6 Class 3

■

O10

GND

I10

Applications

Where EMI filtering in ESD sensitive equipment is

required :

Figure 2. Device configuration

■

LCD for mobile phones

Low-pass Filter

■

Computers and printers

■

Communication systems

Input

Output

■

MCU boards

Description

Ri/o = 70

Cline = 30pF

GND

The EMIF10-LCD02F3 is a 10-line highly

integrated device designed to suppress EMI/RFI

noise in all systems subjected to electromagnetic

interference. The EMIF10 Flip Chip packaging

means the package size is equal to the die size.

This filter includes ESD protection circuitry, which

prevents damage to the protected device when

subjected to ESD surges up 15kV.

TM : IPAD is a trademark of STMicroelectronics.

April 2008

Rev 2

1/8

www.st.com

Characteristics

EMIF10-LCD02F3

Characteristics

Table 1.

Absolute maximum ratings (T amb = 25 °C)

Symbol

Parameter and test conditions

Value

Unit

T j

Maximum junction temperature

125

°C

T op

Operating temperature range

-40 to +85

°C

T stg

Storage temperature range

-55 to 150

°C

Table 2.

Electrical characteristics (T amb = 25 °C)

Symbol

Parameters

V BR

Breakdown voltage

I RM

Leakage current @ V RM

I F

V RM

Stand-off voltage

V F

V CL

Clamping voltage

V CL

V BR

V RM

I RM

I R

I PP

Peak pulse current

R I/O

Series resistance between Input & Output

I PP

C line

Input capacitance per line

Symbol

Test conditions

Min

Typ

Max

Unit

V BR

I R = 1 mA

I RM

V RM = 3 V

200

R 2

Tolerance ± 20%

C line

Vline = 0 V, V OSC = 30 mV, F =1 MHz

2/8

EMIF10-LCD02F3

Characteristics

Figure 3. S21(dB) all lines attenuation

measurement and Aplac simulation

Figure 4. Analog cross talk measurement

0.00

-10.00

-20.00

-30.00

-40.00

-50.00

-60.00

-70.00

-80.00

-90.00

-100.00

100.0k

1.0M

10.0M

100.0M

1.0G

f/Hz

Xtalk 1/2

Figure 5. ESD response to IEC 61000-4-2

(+15 kV air discharge) on one input

and on one output

Figure 6. ESD response to IEC 61000-4-2

(-15 kV air discharge) on one input

and on one output

Input

10V/d

Input

10V/d

Output

10V/d

Output

10V/d

100ns/d

Figure 7. Line capacitance versus applied voltage

C (pF)

line

V (V)

line

3/8

0.00

-10.00

-20.00

-30.00

-40.00

-50.00

-60.00

-70.00

-80.00

-90.00

-100.00

100.0k

1.0M

10.0M

100.0M

1.0G

f/Hz

Xtalk 1/2

Application information

EMIF10-LCD02F3

Application information

Figure 8. Device structure (one cell)

Lbump Rbump

Rline

Rbump

Lbump

MODEL = D1

MODEL = D2

bulk

MODEL = D3

Rbump

Cbump

Lbump

Rgnd

Lgnd

Figure 9. Aplac model variables

aplacvar Rline 70

aplacvar C_d1 15p

aplacvar C_d2 15p

aplacvar C_d3 600p

aplacvar Ls 950pH

aplacvar Rs 150m

aplacvar Lbump 50pH

aplacvar Rbump 20m

aplacvar Cbump 150f

aplacvar Lgnd 50pH

aplacvar Rgnd 100m

aplacvar Rsub 10m

Diode D1

BV=7

IBV=1m

CJO=C_d1

M=0.28

RS=0.1

VJ=0.6

TT=100n

Diode D2

BV=7

IBV=1m

CJO=C_d2

M=0.28

RS=0.1

VJ=0.6

TT=100n

Diode D3

BV=7

IBV=1m

CJO=C_d3

M=0.28

RS=0.01

VJ=0.6

TT=100n

4/8

EMIF10-LCD02F3

Ordering information scheme

Figure 10. Ordering information scheme

EMIF yy - xxx zz F3

EMI Filter

Number of lines

Information

x = resistance value (Ohms)

z = capacitance value / 10 (pF)

3 letters = application

2 digits = version

Package

F = Flip Chip

3 = Lead-free, pitch = 400 µm, bump = 255 µm

Package information

In order to meet environmental requirements, ST offers these devices in ECOPACK ®

packages. These packages have a lead-free second level interconnect. The category of

second level interconnect is marked on the inner box label, in compliance with JEDEC

Standard JESD97. The maximum ratings related to soldering conditions are also marked on

the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at

www.st.com .

Figure 11. Package dimensions

400µm ± 40

255µm± 40

605µm ± 55

185µ m ± 10

1.97mm ± 30µm

5/8

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