10_2.pdf

The Ten Commandments of Excellent

Design—VHDL Code Examples

Peter Chambers

Engineering Fellow

VLSI Technology

This short paper will give you some VHDL

code examples that will help you design

synchronous circuits that work ﬁrst time.

Those Ten Commandments

Just in case you forgot, here are the Ten Commandments of Excellent Design:

1. All state machine outputs shall alwaysbe registered

2. Thou shalt use registers, never latches

3. Thy state machine inputs, including resets, shall be synchronous

4. Beware fast paths lest they bite thine ankles

5. Minimize skew of thine clocks

6. Cross clock domains with the greatest of caution. Synchronize thy sig-

nals!

7. Have no dead states in thy state machines

8. Have no logic with unbroken asynchronous feedback lest the ﬂeas of

myriad Test Engineers infest thee

9. All decode logic must be crafted carefully—eschew asynchronicity

10. Trust not thy simulator—it may beguile thee when thy design is junk

How to Write Ten-Commandment Code

Conforming to the Ten Commandments is not difﬁcult. In this section you’ll see

how to write VHDL (your author doesn’t do Verilog, but the translation is easy)

Ten-Commandment Code

that complies with the rules. Robust design and ﬁrst-silicon success are the

goals!

The philosophy behind Ten-Commandment code is that synthesizers are not to

be trusted too much. Most of the code you will see is close to the structural

level; some more overtly than others.

Most of the code is self-explanatory. It is assumed that the reader is familiar with

VHDL. Signal names are also obvious to anyone “skilled in the art.”

Ten-Commandment Code

How to Create a Flip-Flop

One of the basic primitives that we need to create robust synchronous designs

is the D-type ﬂip-ﬂop. Look at the code in Code Sample 1:

-- VHDL Code for a D-Type Flip-Flop with an

-- Asynchronous Clear

D_Type_Flip_Flop: process(Reset_n, Clock_In)

begin

if (Reset_n = ’0’) then

Q_Output <= ’0’ after 1 ns;

elsif (Clock_In’event and Clock_In = ’1’) then

Q_Output <= D_Input after 1 ns;

end if;

end process D_Type_Flip_Flop;

Code Sample 1.

A D-Type Flip-Flop

This ﬂip-ﬂop has the following properties:

• An asynchronous active-low clear input sets the Q output to zero.

• It is triggered on the rising edge of the clock.

The Ten Commandments of Excellent Design—VHDL Code Examples

Ten-Commandment Code

How to Create a Latch

While the Ten Commandments speciﬁcally forbid the use of latches, there are

still those heretics who will insist on the use of latches. The code to instantiate a

transparent latch is shown in Code Sample 2:

-- VHDL Code for a Transparent Latch

Latch_Data: process(Latch_Open, D_Input)

begin

if (Latch_Open = ’1’) then

Latched_Data <= D_Input;

-- If Latch_Open = 0, then Latched_Data keeps its old value,

-- i.e. the latch is closed.

end if;

end process Latch_Data;

Code Sample 2.

A Transparent Latch

This latch has the following properties:

• A latch control that opens the latch when high (the latch is transparent).

The Ten Commandments of Excellent Design—VHDL Code Examples

Ten-Commandment Code

How to Create a Metastable-

Hardened Flip-Flop

The use of a metastable-hardened ﬂip ﬂop is nothing more than the direct

instantiation of a suitable library element—in this case, a “dfntns” ﬂip-ﬂop. This

is pure structural VHDL. The component declaration is shown in Code

Sample 3:

-- VHDL Code for a Nice Metastable-Hardened Flip-Flop

component dfntns

Port (

CP : In

std_logic;

D : In

std_logic;

Q : Out std_logic

);

end component;

Code Sample 3.

A Metastable-Hardened Flip-Flop, Component

Declaration

To use the ﬂip-ﬂop in your circuit, instantiate it as shown in Code Sample 4:

-- VHDL Code to Instantiate the Metastable-Hardened Flip-Flop

Metastable_Hardened_Flip_Flop_Please: dfntns port map (

D => D_Input,

CP => Clock_In,

Q => Q_Output

);

Code Sample 4.

A Metastable-Hardened Flip-Flop, Instantiation

This ﬂip-ﬂop has the following properties:

• A maximum clock-to-out time under worst-case setup and hold time viola-

tions. This time is available in the library element speciﬁcations.

The Ten Commandments of Excellent Design—VHDL Code Examples

The Care and Feeding of Toggle Signals

Receiving a Toggle Signal

The Ten Commandments paper suggested that a method for exchanging single-

point information across clock domains is by the use of toggle signals. Here, it is

assumed that the toggle event should generate an active-high pulse to pass to a

state machine. Every toggle—rising edge and falling edge—must create the

pulse. In addition, the pulse must be synchronized correctly to the receiver’s

clock. The code to accomplish this is shown in Code Sample 5:

-- VHDL Code to Create a Pulse from an Asynchronous

-- Toggle Signal

-- First, use a metastable-hardened ﬂip-ﬂop to synchronize the

-- toggle input

Metastable_Hardened_Flip_Flop_Please: dfntns port map (

D => Handshake_T,

CP => Clock_In,

Q => Sync_Handshake_T

);

-- Now pass the synchronized toggle through another ﬂip-ﬂop

Toggle_Reg_Proc: process(Clock_In)

begin

if (Clock_In'event and Clock_In = ’1’) then

Reg_Handshake_T <= Sync_Handshake_T after 1 ns;

end if;

end process Toggle_Reg_Proc;

-- Finally XOR the two synchronized signals to create a pulse

Toggle_Pulse <= Reg_Handshake_T xor Sync_Handshake_T;

Code Sample 5.

Receiving a Toggle Signal

When synthesizing this code, remember to use the “ﬁx hold” option so a fast

path doesn’t occur between the two ﬂip-ﬂops in this circuit.

The Ten Commandments of Excellent Design—VHDL Code Examples

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