CQ42_ core I3 laptop717.com.pdf
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AX1 INTEL UMA/DISCRETE SYSTEM DIAGRAM
14.318MHz
CLOCK GEN
+3V/+5V
PG.2
A
A
PG.32
+1.05V/+1.8V
SODIMM1
INTEL
DDR3
Channel A
Max. 4GB
AMD
Arrandale
PG.33
PG.12
CPU Core
PARK-LP
PCI-E x16
HDMI
HDMI
37.5mm X 37.5mm
SODIMM2
PG.21
PG.34
23mm X 23mm
TDP 8W
DDR3
Channel B
989pin PGA
VGA Core/+1.1V
Max. 4GB
CRT
CRT
TDP 35W
PG.22
PG.13
PG.36
LVDS
LVDS
PG.3~6
PG.14~18
+1.5VSUS
PG.20
DDR3 700MHz
VRAM
64Mx16x4,64bit
FDI
DMI
PG.37
B
B
HDMI
Level
Shifter
+1.05VTT
PG.19
SATA0
HDD
PG.35
PG.23
UMA VGACORE
PG.21
SATA1
INTEL PCH
PG.40
ODD
Charger
PG.23
DP Port B
Ibex Peak-m
CRT
LVDS
PG.39
PCI-E x 1
27mm X 25mm
LANE1
LANEO
USB2.0 Ports
X2
Webcam
1071pin FCBGA
LAN
WLAN
C
C
USB 2.0
TDP 5W
RTL8103EL-VB-GR
BT COMBO
PORT10
PG.26
PG.20
10/100
PG.27
PG.31
USB 2.0
PORT0,1
PORT2
PORT4
PORT5
Card Reader
BT
Softbreeze
Stackup
TOP
GND
IN1
IN2
VCC
BOT
KBC
LPC
PG.7~11
RTS5159-GR
EnE KB3926QF D2
PG.29
PG.24
PG.26
KB
TP
ROM
FAN
Azalia
Speaker
Modem
AUDIO
PG.25
CODEC
D
D
HP/MIC
RJ-11
PG.26
ALC270-GR
PROJECT :AX1
PROJECT :AX1
PROJECT :AX1
Analog MIC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PG.26
PG.25
PG.25
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
1A
1A
1A
Date:
Date:
Date:
Wednesday, July 08, 2009
Wednesday, July 08, 2009
Wednesday, July 08, 2009
Sheet
Sheet
Sheet
1
1
1
of
of
of
40
40
40
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
02
25mA
150mA
150mA
Y1
Y1
+3V
+VDDCORE_CLK
+1.05V
+VDDIO_CLK
+3V
+VDDSE_CLK
+3V
L35
*HCB1608KF-181T15_6
XTAL_IN
XTAL_OUT
1
2
L33
HCB1608KF-181T15_6
L37
HCB1608KF-181T15_6
C425
C425
4.7U/6.3V_6
4.7U/6.3V_6
1
2
1
2
C454
C454
0.1U/10V_4
0.1U/10V_4
1
2
C469
C469
4.7U/6.3V_6
4.7U/6.3V_6
14.318MHZ
14.318MHZ
C436
C436
0.1U/10V_4
0.1U/10V_4
C465
C465
0.1U/10V_4
0.1U/10V_4
+1.5V
C435
C435
0.1U/10V_4
0.1U/10V_4
C423
C423
10U/6.3V_6S
10U/6.3V_6S
C480
C480
0.1U/10V_4
0.1U/10V_4
L34
HCB1608KF-181T15_6
C481
C481
0.1U/10V_4
0.1U/10V_4
C460
33P/50V_4
C455
33P/50V_4
R298
*10K/F_4
A
A
C442
C442
*10U/6.3V_8S
*10U/6.3V_8S
C437
C437
0.1U/10V_4
0.1U/10V_4
1
2
Place each 0.1uF cap close to pin
Place each 0.1uF cap close to pin
Place each 0.1uF cap close to pin
CPU_SEL
R300
10K/F_4
0
1
CPU_SEL
CPU0/1=133MHz
(default)
CPU0/1=100MHz
U13
U13
CLK_BUF_BCLK_P
CLK_BUF_BCLK_N
RP24
RP24
*4P2R-S-0
*4P2R-S-0
5
23
4
3
+VDDSE_CLK
CLK_BUF_BCLK_P
<8>
VDD_LCD
CPU-0
29
22
2
1
CLK_BUF_BCLK_N
<8>
VDD_REF
CPU-0#
1
20
+VDDCORE_CLK
VDD_USB
CPU-1
2
1
17
19
VDD_SRC
CPU-1#
C482
C482
*0.047U/10V
*0.047U/10V
24
9LRS3197
9LRS3197
VDD_CPU
+3V
CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#
CLK_BUF_PCIE_3GPLL
CLK_BUF_PCIE_3GPLL#
CLK_BUF_DREFSSCLK
CLK_BUF_DREFSSCLK#
RP27
RP27
*4P2R-S-0
*4P2R-S-0
18
3
2
4
1
3
+VDDIO_CLK
CLK_BUF_DREFCLK
<8>
VDD_CPU_IO
DOT96T_LPR
B
2
1
15
4
B
CLK_BUF_DREFCLK#
<8>
VDD_SRC_IO
DOT96C_LPR
C415
C415
*0.047U/10V
*0.047U/10V
RP25
RP25
*4P2R-S-0
*4P2R-S-0
31
13
2
4
1
3
<8,12,13>
CGDAT_SMB
CLK_BUF_PCIE_3GPLL
<8>
SDATA
SRC-1
R282
1K/F_4
32
14
<8,12,13>
CGCLK_SMB
CLK_BUF_PCIE_3GPLL#
<8>
SCLK
SRC-1#
R279
R279
10K/F_4
10K/F_4
RP26
RP26
*4P2R-S-0
*4P2R-S-0
16
10
2
4
1
3
+3V
CLK_BUF_DREFSSCLK
<8>
CPU_STOP#
SATA
CLK_ICH_14M
R293
R293
33_4
33_4
CPU_SEL
30
11
<8>
CLK_ICH_14M
CLK_BUF_DREFSSCLK#
<8>
REF_0/CPU_SEL
SATA#
C477
C477
*10P/50V_4
*10P/50V_4
CK_PWRGD_R
CK_PWRGD_R
CLK_VGA_27M_NOSS
25
6
R304
R304
22_4
22_4
EVGA-XTALI
<15>
CK_PW RGD/PD#_3.3
27MHz_nonSS
Place R8044 within 0.5" of C/G
0918 SI Modify
R494
R494
22_4
22_4
7
27M_TCK
<15>
27MHz_SS
XTAL_OUT
Q15
2N7002E
27
XOUT
XTAL_IN
QFN32
QFN32
CLK_VGA_27M_SS
R303
R303
*33_4
*33_4
28
33
CLK_27M_SS
<15>
XIN
GND
R280
100K/F_4
9
26
VSS_SATA
VSS_REF
Discrete only
2
21
2
<34>
VR_PWRGD_CLKEN#
VSS_USB
VSS_CPU
8
12
VSS_LCD
VSS_SRC
9LRS3197
9LRS3197
+3V
EMI request
+1.05V
C
C
+1.05V
<7,8,9,11,13,33,34,40>
+1.5V
<31,38>
+3V
<3,7,8,9,10,11,12,13,15,20,21,22,23,24,25,26,27,28,29,30,31,34,38>
CPU
GPU
PAD0
PAD0
PAD1
PAD1
PAD2
PAD2
PAD3
PAD3
PAD4
PAD4
PAD5
PAD5
PAD6
PAD6
PAD7
PAD7
PAD8
PAD8
H6
H4
H3
H11
H10
H9
H0
H1
H2
H5
H7
H8
H12
H18
D
D
H13
H16
H17
PROJECT :AX1
PROJECT :AX1
PROJECT :AX1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Clock Gen(9LRS3197)/HOLES
Clock Gen(9LRS3197)/HOLES
Clock Gen(9LRS3197)/HOLES
1A
1A
1A
Date:
Date:
Date:
Thursday, November 12, 2009
Thursday, November 12, 2009
Thursday, November 12, 2009
Sheet
Sheet
Sheet
2
2
2
of
of
of
40
40
40
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DIS
UMA
0 ohm
NA
03
Ra
Rb
NA
0 ohm
U16A
U16A
B26
PEG_COMP
R346
R346
49.9/F_4
49.9/F_4
PEG_ICOMPI
A26
Rc
0 ohm
NA
PEG_ICOMPO
A24
B27
<9>
DMI_TXN0
DMI_RX#[0]
PEG_RCOMPO
C23
A25
PEG_RBIAS
R345
R345
750/F_4
750/F_4
<9>
DMI_TXN1
DMI_RX#[1]
PEG_RBIAS
B22
<9>
DMI_TXN2
DMI_RX#[2]
PEG_RX#[0..15]
<14>
A21
K35
PEG_RX#0
U16B
U16B
<9>
DMI_TXN3
DMI_RX#[3]
PEG_RX#[0]
J34
PEG_RX#1
R163
R163
20/F_4
20/F_4
H_COMP3
AT23
A16
PEG_RX#[1]
COMP3
BCLK
CLK_CPU_BCLK
<10>
B24
J33
PEG_RX#2
PEG_RX#3
R164
R164
20/F_4
20/F_4
H_COMP2
AT24
B16
<9>
DMI_TXP0
DMI_RX[0]
PEG_RX#[2]
COMP2
BCLK#
CLK_CPU_BCLK#
<10>
H_COMP1
D23
G35
R51
R51
49.9/F_4
49.9/F_4
G16
MISC
MISC
A
<9>
DMI_TXP1
DMI_RX[1]
PEG_RX#[3]
COMP1
BCLK_ITP_P
<30>
A
PEG_RX#4
PEG_RX#5
H_COMP0
B23
G32
R165
R165
49.9/F_4
49.9/F_4
AT26
AR30
For ITP CLk
<9>
DMI_TXP2
DMI_RX[2]
PEG_RX#[4]
COMP0
BCLK_ITP
BCLK_ITP_N
<30>
A22
F34
AH24
AT30
<9>
DMI_TXP3
CLK_PCIE_3GPLL
<8>
DMI_RX[3]
PEG_RX#[5]
SKTOCC#
BCLK_ITP#
PEG_RX#6
F31
CLK_PCIE_3GPLL#
<8>
PEG_RX#[6]
DMI
DMI
PEG_RX#7
CLOCKS
CLOCKS
Rc
D24
D35
E16
<9>
DMI_RXN0
DMI_TX#[0]
PEG_RX#[7]
PEG_CLK
PEG_RX#8
PEG_RX#9
H_CATERR#
R351
R351
0_4
0_4
G24
E33
AK14
D16
<9>
DMI_RXN1
DMI_TX#[1]
PEG_RX#[8]
CATERR#
PEG_CLK#
DREFSSCLK_R
Ra
F23
C33
AT15
<9>
DMI_RXN2
<10>
H_PROCHOT#
H_PECI
DMI_TX#[2]
PEG_RX#[9]
PECI
PEG_RX#10
THERMAL
THERMAL
R343
R343
*0_4P2R_4
*0_4P2R_4
H23
D32
AN26
A18
3
4
<9>
DMI_RXN3
<29,34>
PM_THRMTRIP#
DREFSSCLK
<8>
DMI_TX#[3]
PEG_RX#[10]
PROCHOT#
DPLL_REF_SSCLK
PEG_RX#11
B32
AK15
A17
1
2
<10,29>
DREFSSCLK#
<8>
PEG_RX#[11]
THERMTRIP#
DPLL_REF_SSCLK#
PEG_RX#12
Rb
D25
C31
<9>
DMI_RXP0
DMI_TX[0]
PEG_RX#[12]
PEG_RX#13
DREFSSCLK#_R
R350
R350
0_4
0_4
F24
B28
<9>
DMI_RXP1
DMI_TX[1]
PEG_RX#[13]
PEG_RX#14
DDR3_DRAMRST#_C
E23
B30
AP26
F6
<9>
DMI_RXP2
<30>
H_CPURST#
DMI_TX[2]
PEG_RX#[14]
RESET_OBS#
SM_DRAMRST#
PEG_RX#15
PEG_RX0
G23
A31
AL15
<9>
DMI_RXP3
<9>
PM_SYNC
DDR3
MISC
DDR3
MISC
DMI_TX[3]
PEG_RX#[15]
PM_SYNC
SM_RCOMP_0
SM_RCOMP_1
R423
R423
100/F_4
100/F_4
AN14
AL1
PEG_RX[0..15]
<14>
VCCPWRGOOD_1
SM_RCOMP[0]
R424
R424
24.9/F_4
24.9/F_4
J35
AN27
AM1
<10,30>
PM_DRAM_PW RGD
H_PW RGOOD
PEG_RX[0]
VCCPWRGOOD_0
SM_RCOMP[1]
2.7GT/s data rate
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
SM_RCOMP_2
R425
R425
130/F_4
130/F_4
H34
AK13
AN1
<9>
PEG_RX[1]
SM_DRAMPWROK
SM_RCOMP[2]
R194
R194
10K/J_4
10K/J_4
H33
+1.05V_VTT
<9>
FDI_TXN[7:0]
PEG_RX[2]
FDI_TXN0
FDI_TXN1
FDI_TXN3
FDI_TXN4
FDI_TXN5
PM_EXT_TS#0
PM_EXT_TS#1
R190
R190
*0/short_4
*0/short_4
E22
F35
AM26
AN15
<30>
H_PW RGD_XDP
PM_EXTTS#0 <12,13>
FDI_TX#[0]
PEG_RX[3]
TAPPWRGOOD
PM_EXT_TS#[0]
D21
G33
AP15
R189
R189
*0/short_4
*0/short_4
PM_EXTTS#1 <13>
FDI_TX#[1]
PEG_RX[4]
PM_EXT_TS#[1]
FDI_TXN2
H_VTTPW RGD
CPU_PLTRST#
R202
R202
10K/J_4
10K/J_4
D19
E34
AM15
+1.05V_VTT
FDI_TX#[2]
PEG_RX[5]
VTTPWRGOOD
D18
F32
AL14
<8,27,29,30,31>
PLTRST#
FDI_TX#[3]
PEG_RX[6]
RSTIN#
G21
D34
R153
R153
1.5K/F_4
1.5K/F_4
AT28
XDP_PRDY# <30>
XDP_PREQ# <30>
FDI_TX#[4]
PEG_RX[7]
PRDY#
E19
F33
PEG_RX8
PEG_RX9
AP27
FDI_TX#[5]
PEG_RX[8]
PREQ#
FDI_TXN6
FDI_TXN7
F21
B33
R157
R157
750/F_4
750/F_4
PWR MANAGEMENT
PWR MANAGEMENT
AN28
FDI_TX#[6]
PEG_RX[9]
TCK
XDP_TCLK <30>
XDP_TMS <30>
XDP_TRST# <30>
G18
D31
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX14
T20
T20
FDI_TX#[7]
PEG_RX[10]
A32
AP28
PEG_RX[11]
TMS
C30
<9>
FDI_TXP[7:0]
PEG_RX[12]
T21
T21
FDI_TXP0
FDI_TXP1
D22
A28
PEG_RX13
JTAG & BPM
JTAG & BPM
AT27
FDI_TX[0]
PEG_RX[13]
<30>
XDP_OBS[0:7]
TRST#
C21
B29
XDP_OBS0
AJ22
FDI_TX[1]
PEG_RX[14]
BPM#[0]
T26
T26
FDI_TXP2
D20
A30
PEG_RX15
XDP_OBS1
AK22
AT29
XDP_TDI_R
B
FDI_TX[2]
PEG_RX[15]
BPM#[1]
TDI
T27
T27
B
FDI_TXP3
FDI_TXP4
C18
XDP_OBS2
AK24
AR27
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
FDI_TX[3]
PEG_TX#[0..15]
<14>
BPM#[2]
TDO
T25
T25
C_PEG_TX#0
PEG_TX#0
XDP_OBS3
G22
L33
C622
C622
0.1U/10V_4
0.1U/10V_4
AJ24
AR29
FDI_TX[4]
PEG_TX#[0]
BPM#[3]
TDI_M
T24
T24
FDI_TXP5
C_PEG_TX#1
C617
C617
0.1U/10V_4
0.1U/10V_4
PEG_TX#1
PEG_TX#2
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
E20
M35
AJ25
AP29
FDI_TX[5]
PEG_TX#[1]
BPM#[4]
TDO_M
T23
T23
FDI_TXP6
C_PEG_TX#2
F20
M33
C613
C613
0.1U/10V_4
0.1U/10V_4
AH22
FDI_TX[6]
PEG_TX#[2]
BPM#[5]
FDI_TXP7
C_PEG_TX#3
C609
C609
0.1U/10V_4
0.1U/10V_4
PEG_TX#3
PEG_TX#4
G19
M30
AK23
FDI_TX[7]
PEG_TX#[3]
BPM#[6]
C_PEG_TX#4
C604
C604
0.1U/10V_4
0.1U/10V_4
L31
AH23
AN25
XDP_DBRESET# <9,30>
PEG_TX#[4]
BPM#[7]
DBR#
C_PEG_TX#5
C594
C594
0.1U/10V_4
0.1U/10V_4
PEG_TX#5
PEG_TX#6
PEG_TX#7
F17
K32
<9>
FDI_FSYNC0
FDI_FSYNC[0]
PEG_TX#[5]
C_PEG_TX#6
C589
C589
0.1U/10V_4
0.1U/10V_4
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
E17
M29
<9>
FDI_FSYNC1
FDI_FSYNC[1]
PEG_TX#[6]
C_PEG_TX#7
C586
C586
0.1U/10V_4
0.1U/10V_4
J31
PEG_TX#[7]
C_PEG_TX#8
C579
C579
0.1U/10V_4
0.1U/10V_4
PEG_TX#8
C17
K29
<9>
FDI_INT
FDI_INT
PEG_TX#[8]
C_PEG_TX#9
C573
C573
0.1U/10V_4
0.1U/10V_4
PEG_TX#9
H30
PEG_TX#[9]
C_PEG_TX#10
C569
C569
0.1U/10V_4
0.1U/10V_4
PEG_TX#10
PEG_TX#11
F18
H29
<9>
FDI_LSYNC0
FDI_LSYNC[0]
PEG_TX#[10]
C_PEG_TX#11
C566
C566
0.1U/10V_4
0.1U/10V_4
D17
F29
<9>
FDI_LSYNC1
FDI_LSYNC[1]
PEG_TX#[11]
C_PEG_TX#12
C563
C563
0.1U/10V_4
0.1U/10V_4
PEG_TX#12
E28
PEG_TX#[12]
C_PEG_TX#13
C561
C561
0.1U/10V_4
0.1U/10V_4
PEG_TX#13
D29
PEG_TX#[13]
C_PEG_TX#14
C558
C558
0.1U/10V_4
0.1U/10V_4
PEG_TX#14
D27
PEG_TX#[14]
C_PEG_TX#15
C555
C555
0.1U/10V_4
0.1U/10V_4
PEG_TX#15
C26
PEG_TX#[15]
JTAG MAPPING
PEG_TX[0..15]
<14>
+1.05V_VTT
C_PEG_TX0
C619
C619
0.1U/10V_4
0.1U/10V_4
PEG_TX0
L34
PEG_TX[0]
C_PEG_TX1
C615
C615
0.1U/10V_4
0.1U/10V_4
PEG_TX1
PEG_TX2
M34
PEG_TX[1]
M32
C_PEG_TX2
C610
C610
0.1U/10V_4
0.1U/10V_4
XDP_TDO
H_CATERR#
R174
R174
51/J_4
51/J_4
PEG_TX[2]
L30
C_PEG_TX3
C607
C607
0.1U/10V_4
0.1U/10V_4
PEG_TX3
PEG_TX4
R130
R130
49.9/F_4
49.9/F_4
PEG_TX[3]
M31
C_PEG_TX4
C595
C595
0.1U/10V_4
0.1U/10V_4
H_PROCHOT#
CPU_PLTRST#
R140
R140
56.2/F_4
56.2/F_4
PEG_TX[4]
K31
C_PEG_TX5
C591
C591
0.1U/10V_4
0.1U/10V_4
PEG_TX5
PEG_TX6
PEG_TX7
R147
R147
*68/J_4
*68/J_4
XDP_TDI_R
Ra
Rb
Rc
R168
R168
0/J_4
0/J_4
XDP_TDI
<30>
PEG_TX[5]
M28
C_PEG_TX6
C587
C587
0.1U/10V_4
0.1U/10V_4
XDP_TMS
R159
R159
*51/J_4
*51/J_4
XDP_TDO_M
R158
R158
*0/J_4
*0/J_4
XDP_TDO
<30>
PEG_TX[6]
H31
C_PEG_TX7
C582
C582
0.1U/10V_4
0.1U/10V_4
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
R178
R178
*51/J_4
*51/J_4
PEG_TX[7]
K28
C_PEG_TX8
C575
C575
0.1U/10V_4
0.1U/10V_4
PEG_TX8
PEG_TX10
R167
R167
*51/J_4
*51/J_4
PEG_TX[8]
G30
C_PEG_TX9
C570
C570
0.1U/10V_4
0.1U/10V_4
PEG_TX9
R162
0/J_4
PEG_TX[9]
G29
C_PEG_TX10
C567
C567
0.1U/10V_4
0.1U/10V_4
R154
R154
*51/J_4
*51/J_4
C
PEG_TX[10]
C
F28
C_PEG_TX11
C564
C564
0.1U/10V_4
0.1U/10V_4
PEG_TX11
PEG_TX[11]
E27
C_PEG_TX12
C562
C562
0.1U/10V_4
0.1U/10V_4
PEG_TX12
PEG_TX[12]
C_PEG_TX13
PEG_TX13
XDP_TDI_M
XDP_TDO_R
D28
C559
C559
0.1U/10V_4
0.1U/10V_4
R
Re
R161
R161
*0/J_4
*0/J_4
PEG_TX[13]
C27
C_PEG_TX14
C556
C556
0.1U/10V_4
0.1U/10V_4
PEG_TX14
R175
R175
0/J_4
0/J_4
PEG_TX[14]
C_PEG_TX15
PEG_TX15
C25
C554
C554
0.1U/10V_4
0.1U/10V_4
PEG_TX[15]
+3V
XDP_TRST#
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
U9
MC74VHC1G08DFT2G
R191
2K/F_4
R177
51/J_4
2
1
HW PG_1
H_VTTPW RGD
4
<29,30,32,33,35,36,37,40>
HW PG
for S3 power reduction
R197
1K/F_4
R58
R58
*0_4
*0_4
Q8
Q8
BSS138_NL
BSS138_NL
3
+3VS5
+1.5VSUS
DDR3_DRAMRST#_C
1
DDR3_DRAMRST#
<12,13>
Scan Chain
(Default)
STUFF -> Ra, Rc, Re
NO STUFF -> Rb, Rd
Discrete Only
SI modify
R54
R54
1K/F_4
1K/F_4
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
R65
R65
SI modify
R176
*0_4
R55
R55
0_4
0_4
CPU Only
STUFF -> Ra, Rb
NO STUFF -> Rc, Rd, Re
R53
R53
0_4
0_4
R559
*10K/F_4
R558
*8.25K/F_4
PCIE_CLK_REQ7#
<10>
R56
R56
0_4
0_4
100K/F_4
100K/F_4
*0_4/S
*0_4/S
R52
R52
1K/F_4
1K/F_4
R554
R554
*0_4
*0_4
R179
R179
HW PG_1
STUFF -> Rd, Re
NO STUFF -> Ra, Rb, Rc
R560
R560
10K/F_4
10K/F_4
1
GMCH Only
D
D
FDI_FSYNC can
gang all these
4 signals
together and
tie them with
only one 1K
resistor to GND
( Check list
1.0 ).
C823
0.047U/16V_4
2
2
1
R166
1.5K/F_4
+3VS5
4
<35>
STAT_1.1
PM_DRAM_PW RGD
PROJECT :AX1
PROJECT :AX1
PROJECT :AX1
U29
*MC74VHC1G08DFT2G
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
R160
750/F_4
Use a voltage divider with VDDQ (1.5 V) rail
ON in S3) and resistor combination of 1.5K ±1%
(to VDDQ)/750±1% (to GND) to convert to
processor VTT level.
<5,10,11,29,30,34,35,40>
+1.05V_VTT
<5,12,13,37,38>
+1.5VSUS
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
<2,7,8,9,10,11,12,13,15,20,21,22,23,24,25,26,27,28,29,30,31,34,38>
+3V
Custom
Custom
Custom
1A
1A
1A
PROCESSER 1/4(HOST&PEX)
PROCESSER 1/4(HOST&PEX)
PROCESSER 1/4(HOST&PEX)
Date:
Date:
Date:
Monday, November 30, 2009
Monday, November 30, 2009
Monday, November 30, 2009
Sheet
Sheet
Sheet
3
3
3
of
of
of
40
40
40
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
04
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)
A
A
<13>
M_B_DQ[63:0]
U16C
U16C
U16D
U16D
<12>
M_A_DQ[63:0]
M_A_DQ0
M_B_DQ0
A10
AA6
B5
W8
M_A_CLK0 <12>
M_A_CLK0# <12>
M_A_CKE0 <12>
M_B_CLK0
<13>
SA_DQ[0]
SA_CK[0]
SB_DQ[0]
SB_CK[0]
M_A_DQ1
M_B_DQ1
C10
AA7
A5
W9
M_B_CLK0# <13>
M_B_CKE0
SA_DQ[1]
SA_CK#[0]
SB_DQ[1]
SB_CK#[0]
M_A_DQ2
M_B_DQ2
M_B_DQ3
C7
P7
C3
M3
<13>
SA_DQ[2]
SA_CKE[0]
SB_DQ[2]
SB_CKE[0]
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
A7
B3
SA_DQ[3]
SB_DQ[3]
M_B_DQ4
M_B_DQ5
B10
Y6
E4
V7
M_A_CLK1 <12>
M_B_CLK1
<13>
SA_DQ[4]
SA_CK[1]
SB_DQ[4]
SB_CK[1]
D10
Y5
A6
V6
M_A_CLK1# <12>
M_A_CKE1 <12>
M_B_CLK1# <13>
M_B_CKE1
SA_DQ[5]
SA_CK#[1]
SB_DQ[5]
SB_CK#[1]
M_B_DQ6
M_B_DQ7
E10
P6
A4
M2
<13>
SA_DQ[6]
SA_CKE[1]
SB_DQ[6]
SB_CKE[1]
M_A_DQ7
A8
C4
SA_DQ[7]
SB_DQ[7]
M_A_DQ8
M_A_DQ9
M_B_DQ8
M_B_DQ9
D8
AE2
D1
AB8
M_A_CS#0 <12>
M_A_CS#1 <12>
M_B_CS#0
<13>
SA_DQ[8]
SA_CS#[0]
SB_DQ[8]
SB_CS#[0]
F10
AE8
D2
AD6
M_B_CS#1
<13>
SA_DQ[9]
SA_CS#[1]
SB_DQ[9]
SB_CS#[1]
M_A_DQ10
M_A_DQ11
M_A_DQ13
M_B_DQ10
M_B_DQ11
M_B_DQ13
E6
F2
SA_DQ[10]
SB_DQ[10]
F7
AD8
F1
AC7
M_A_ODT0 <12>
M_A_ODT1 <12>
M_B_ODT0 <13>
M_B_DM[7:0]
SA_DQ[11]
SA_ODT[0]
SB_DQ[11]
SB_ODT[0]
M_A_DQ12
M_A_DQ14
M_A_DQ15
M_B_DQ12
E9
AF9
C2
AD1
M_B_ODT1 <13>
SA_DQ[12]
SA_ODT[1]
SB_DQ[12]
SB_ODT[1]
B7
F5
M_A_DM[7:0]
<12>
<13>
SA_DQ[13]
SB_DQ[13]
M_A_DM0
M_B_DQ14
M_B_DM0
E7
B9
F3
D4
SA_DQ[14]
SA_DM[0]
SB_DQ[14]
SB_DM[0]
C6
D7
M_A_DM1
DM signals are not present on Clarkfield
processor. All DM signal can be left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only
M_B_DQ15
G4
E1
M_B_DM1
DM signals are not present on Clarkfield
processor. All DM signal can be left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only
SA_DQ[15]
SA_DM[1]
SB_DQ[15]
SB_DM[1]
M_A_DQ16
M_A_DQ17
M_A_DM2
M_B_DQ16
M_B_DM2
H10
H7
H6
H3
SA_DQ[16]
SA_DM[2]
SB_DQ[16]
SB_DM[2]
G8
M7
M_A_DM3
M_B_DQ17
G2
K1
M_B_DM3
SA_DQ[17]
SA_DM[3]
SB_DQ[17]
SB_DM[3]
M_A_DQ18
M_A_DQ19
M_A_DQ21
K7
AG6
M_A_DM4
M_B_DQ18
M_B_DQ19
M_B_DQ21
J6
AH1
M_B_DM4
SA_DQ[18]
SA_DM[4]
SB_DQ[18]
SB_DM[4]
J8
AM7
M_A_DM5
M_A_DM6
J3
AL2
M_B_DM5
M_B_DM6
SA_DQ[19]
SA_DM[5]
SB_DQ[19]
SB_DM[5]
M_A_DQ20
M_A_DQ22
M_A_DQ23
M_A_DQ24
G7
AN10
M_B_DQ20
G1
AR4
SA_DQ[20]
SA_DM[6]
SB_DQ[20]
SB_DM[6]
G10
AN13
M_A_DM7
G5
AT8
M_B_DM7
SA_DQ[21]
SA_DM[7]
SB_DQ[21]
SB_DM[7]
J7
M_B_DQ22
J2
SA_DQ[22]
M_A_DQS#[7:0]
<12>
SB_DQ[22]
M_B_DQS#[7:0]
<13>
J10
C9
M_A_DQS#0
M_B_DQ23
J1
D5
M_B_DQS#0
SA_DQ[23]
SA_DQS#[0]
SB_DQ[23]
SB_DQS#[0]
L7
F8
M_A_DQS#1
M_B_DQ24
J5
F4
M_B_DQS#1
SA_DQ[24]
SA_DQS#[1]
SB_DQ[24]
SB_DQS#[1]
M_A_DQ25
M6
J9
M_A_DQS#2
M_B_DQ25
K2
J4
M_B_DQS#2
SA_DQ[25]
SA_DQS#[2]
SB_DQ[25]
SB_DQS#[2]
M_A_DQ26
M8
N9
M_A_DQS#3
M_B_DQ26
L3
L4
M_B_DQS#3
B
SA_DQ[26]
SA_DQS#[3]
SB_DQ[26]
SB_DQS#[3]
B
M_A_DQ27
L9
AH7
M_A_DQS#4
M_B_DQ27
M1
AH2
M_B_DQS#4
SA_DQ[27]
SA_DQS#[4]
SB_DQ[27]
SB_DQS#[4]
M_A_DQ28
M_A_DQ29
M_A_DQS#5
M_A_DQS#6
M_B_DQ28
M_B_DQ29
M_B_DQS#5
M_B_DQS#6
L6
AK9
K5
AL4
SA_DQ[28]
SA_DQS#[5]
SB_DQ[28]
SB_DQS#[5]
K8
AP11
K4
AR5
SA_DQ[29]
SA_DQS#[6]
SB_DQ[29]
SB_DQS#[6]
M_A_DQ30
M_A_DQS#7
M_B_DQ30
M_B_DQ31
M_B_DQS#7
N8
AT13
M4
AR8
SA_DQ[30]
SA_DQS#[7]
SB_DQ[30]
SB_DQS#[7]
M_A_DQ31
P9
N5
M_A_DQS[7:0]
<12>
M_B_DQS[7:0]
<13>
SA_DQ[31]
SB_DQ[31]
M_A_DQ32
M_A_DQS0
M_B_DQ32
M_B_DQS0
AH5
C8
AF3
C5
SA_DQ[32]
SA_DQS[0]
SB_DQ[32]
SB_DQS[0]
M_A_DQ33
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_B_DQ33
M_B_DQS1
AF5
F9
AG1
E3
SA_DQ[33]
SA_DQS[1]
SB_DQ[33]
SB_DQS[1]
M_A_DQ34
M_A_DQ35
M_A_DQ37
M_B_DQ34
M_B_DQ35
M_B_DQ37
M_B_DQS2
AK6
H9
AJ3
H4
SA_DQ[34]
SA_DQS[2]
SB_DQ[34]
SB_DQS[2]
M_B_DQS3
AK7
M9
AK1
M5
SA_DQ[35]
SA_DQS[3]
SB_DQ[35]
SB_DQS[3]
M_A_DQ36
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQS4
M_A_DQS6
M_B_DQ36
M_B_DQS4
AF6
AH8
AG4
AG2
SA_DQ[36]
SA_DQS[4]
SB_DQ[36]
SB_DQS[4]
M_A_DQS5
M_A_DQS7
M_B_DQS5
M_B_DQS6
AG5
AK10
AG3
AL5
SA_DQ[37]
SA_DQS[5]
SB_DQ[37]
SB_DQS[5]
M_B_DQ38
AJ7
AN11
AJ4
AP5
SA_DQ[38]
SA_DQS[6]
SB_DQ[38]
SB_DQS[6]
M_B_DQ39
M_B_DQS7
AJ6
AR13
AH4
AR7
SA_DQ[39]
SA_DQS[7]
SB_DQ[39]
SB_DQS[7]
M_B_DQ40
AJ10
AK3
M_A_A[15:0]
<12>
M_B_A[15:0]
<13>
SA_DQ[40]
SB_DQ[40]
M_A_DQ41
M_A_A0
M_B_DQ41
M_B_A0
AJ9
Y3
AK4
U5
SA_DQ[41]
SA_MA[0]
SB_DQ[41]
SB_MA[0]
M_A_DQ42
M_A_A1
M_B_DQ42
M_B_A1
AL10
W1
AM6
V2
SA_DQ[42]
SA_MA[1]
SB_DQ[42]
SB_MA[1]
M_A_DQ43
M_A_A2
M_A_A3
M_B_DQ43
M_B_A2
M_B_A3
AK12
AA8
AN2
T5
SA_DQ[43]
SA_MA[2]
SB_DQ[43]
SB_MA[2]
M_A_DQ44
M_A_DQ45
M_B_DQ44
M_B_DQ45
AK8
AA3
AK5
V3
SA_DQ[44]
SA_MA[3]
SB_DQ[44]
SB_MA[3]
M_A_A4
M_B_A4
AL7
V1
AK2
R1
SA_DQ[45]
SA_MA[4]
SB_DQ[45]
SB_MA[4]
M_A_DQ46
M_A_A5
M_A_A6
M_A_A7
M_B_DQ46
M_B_DQ47
M_B_A5
M_B_A6
AK11
AA9
AM4
T8
SA_DQ[46]
SA_MA[5]
SB_DQ[46]
SB_MA[5]
M_A_DQ47
AL8
V8
AM3
R2
SA_DQ[47]
SA_MA[6]
SB_DQ[47]
SB_MA[6]
M_A_DQ48
AN8
T1
M_B_DQ48
AP3
R6
M_B_A7
SA_DQ[48]
SA_MA[7]
SB_DQ[48]
SB_MA[7]
M_A_DQ49
AM10
Y9
M_A_A8
M_B_DQ49
AN5
R4
M_B_A8
SA_DQ[49]
SA_MA[8]
SB_DQ[49]
SB_MA[8]
M_A_DQ50
AR11
U6
M_A_A9
M_A_A10
M_A_A11
M_B_DQ50
AT4
R5
M_B_A9
M_B_A10
M_B_A11
SA_DQ[50]
SA_MA[9]
SB_DQ[50]
SB_MA[9]
M_A_DQ51
AL11
AD4
M_B_DQ51
AN6
AB5
SA_DQ[51]
SA_MA[10]
SB_DQ[51]
SB_MA[10]
M_A_DQ52
M_A_DQ53
AM9
T2
M_B_DQ52
AN4
P3
SA_DQ[52]
SA_MA[11]
SB_DQ[52]
SB_MA[11]
AN9
U3
M_A_A12
M_B_DQ53
AN3
R3
M_B_A12
SA_DQ[53]
SA_MA[12]
SB_DQ[53]
SB_MA[12]
M_A_DQ54
AT11
AG8
M_A_A13
M_B_DQ54
M_B_DQ55
AT5
AF7
M_B_A13
SA_DQ[54]
SA_MA[13]
SB_DQ[54]
SB_MA[13]
M_A_DQ55
AP12
T3
M_A_A14
AT6
P5
M_B_A14
C
SA_DQ[55]
SA_MA[14]
SB_DQ[55]
SB_MA[14]
C
M_A_DQ56
AM12
V9
M_A_A15
M_B_DQ56
M_B_DQ57
AN7
N1
M_B_A15
SA_DQ[56]
SA_MA[15]
SB_DQ[56]
SB_MA[15]
M_A_DQ57
AN12
AP6
SA_DQ[57]
SB_DQ[57]
M_A_DQ58
M_A_DQ59
M_A_DQ61
M_B_DQ58
M_B_DQ59
M_B_DQ61
AM13
AP8
SA_DQ[58]
SB_DQ[58]
AT14
AT9
SA_DQ[59]
SB_DQ[59]
M_A_DQ60
M_A_DQ62
M_A_DQ63
M_B_DQ60
AT12
AT7
SA_DQ[60]
SB_DQ[60]
AL13
AP9
SA_DQ[61]
SB_DQ[61]
M_B_DQ62
AR14
AR10
SA_DQ[62]
SB_DQ[62]
M_B_DQ63
AP14
AT10
SA_DQ[63]
SB_DQ[63]
AC3
AB1
<12>
M_A_BS#0
<13>
M_B_BS#0
SA_BS[0]
SB_BS[0]
AB2
W5
<12>
M_A_BS#1
<13>
M_B_BS#1
SA_BS[1]
SB_BS[1]
U7
R7
<12>
M_A_BS#2
<13>
M_B_BS#2
SA_BS[2]
SB_BS[2]
AE1
AC5
<12>
M_A_CAS#
<13>
M_B_CAS#
SA_CAS#
SB_CAS#
AB3
Y7
<12>
M_A_RAS#
<13>
M_B_RAS#
SA_RAS#
SB_RAS#
AE9
AC6
<12>
M_A_W E#
<13>
M_B_W E#
SA_WE#
SB_WE#
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
D
D
PROJECT :AX1
PROJECT :AX1
PROJECT :AX1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
1A
1A
1A
PROCESSER 2/4(DDR)
PROCESSER 2/4(DDR)
PROCESSER 2/4(DDR)
Date:
Date:
Date:
Thursday, November 12, 2009
Thursday, November 12, 2009
Thursday, November 12, 2009
Sheet
Sheet
Sheet
4
4
4
of
of
of
40
40
40
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
05
18A
U16F
U16F
DIS
UMA
AG35
AH14
+VCORE
+1.05V_VTT
VCC1
VTT0_1
C147
C147
22U/6.3V_8S
22U/6.3V_8S
AG34
AH12
Rc
Rd
NA
4.7K
VCC2
VTT0_2
C25
C25
22U/6.3V_8S
22U/6.3V_8S
AG33
AH11
C637
C637
10U/6.3V_8
10U/6.3V_8
VCC3
VTT0_3
C639
C639
22U/6.3V_8S
22U/6.3V_8S
AG32
AH10
C625
C625
10U/6.3V_8
10U/6.3V_8
NA
0 ohm
0 ohm
VCC4
VTT0_4
C538
C538
22U/6.3V_8S
22U/6.3V_8S
C597
C597
10U/6.3V_8
10U/6.3V_8
AG31
J14
VCC5
VTT0_5
C184
C184
22U/6.3V_8S
22U/6.3V_8S
C531
C531
10U/6.3V_8
10U/6.3V_8
Re
Rf
NA
AG30
J13
VCC6
VTT0_6
C144
C144
22U/6.3V_8S
22U/6.3V_8S
C47
C47
10U/6.3V_8
10U/6.3V_8
AG29
H14
VCC7
VTT0_7
NA
NA
C148
C148
22U/6.3V_8S
22U/6.3V_8S
AG28
H12
C605
C605
10U/6.3V_8
10U/6.3V_8
VCC8
VTT0_8
C236
C236
22U/6.3V_8S
22U/6.3V_8S
AG27
G14
C52
C52
10U/6.3V_8
10U/6.3V_8
U16G
U16G
VCC9
VTT0_9
A
A
C627
C627
22U/6.3V_8S
22U/6.3V_8S
AG26
G13
C645
C645
22U/6.3V_8S
22U/6.3V_8S
VCC10
VTT0_10
C170
C170
22U/6.3V_8S
22U/6.3V_8S
C105
C105
22U/6.3V_8S
22U/6.3V_8S
AF35
G12
AT21
VCC11
VTT0_11
VAXG1
C169
C169
22U/6.3V_8S
22U/6.3V_8S
C630
C630
22U/6.3V_8S
22U/6.3V_8S
AF34
G11
AT19
AR22
VCC_AXG_SENSE
<40>
VCC12
VTT0_12
VAXG2
VAXG_SENSE
C654
C654
22U/6.3V_8S
22U/6.3V_8S
AF33
F14
AT18
AT22
VSS_AXG_SENSE
<40>
VCC13
VTT0_13
VAXG3
VSSAXG_SENSE
C631
C631
10U/6.3V_8
10U/6.3V_8
AF32
F13
AT16
VCC14
VTT0_14
VAXG4
C204
C204
10U/6.3V_8
10U/6.3V_8
AF31
F12
AR21
VCC15
VTT0_15
VAXG5
C186
C186
10U/6.3V_8
10U/6.3V_8
AF30
F11
AR19
VCC16
VTT0_16
VAXG6
C537
C537
10U/6.3V_8
10U/6.3V_8
AF29
E14
AR18
VCC17
VTT0_17
VAXG7
C202
C202
10U/6.3V_8
10U/6.3V_8
AF28
E12
AR16
AM22
GFXVR_VID_0
<40>
VCC18
VTT0_18
VAXG8
GFX_VID[0]
C146
C146
10U/6.3V_8
10U/6.3V_8
AF27
D14
AP21
AP22
GFXVR_VID_1
<40>
VCC19
VTT0_19
VAXG9
GFX_VID[1]
C30
C30
10U/6.3V_8
10U/6.3V_8
AF26
D13
AP19
AN22
GFXVR_VID_2
<40>
VCC20
VTT0_20
VAXG10
GFX_VID[2]
C235
C235
10U/6.3V_8
10U/6.3V_8
AD35
D12
AP18
AP23
VCC21
VTT0_21
VAXG11
GFX_VID[3]
GFXVR_VID_3
<40>
C171
C171
10U/6.3V_8
10U/6.3V_8
AD34
D11
UMA only
AP16
AM23
VCC22
VTT0_22
VAXG12
GFX_VID[4]
GFXVR_VID_4
<40>
C238
C238
10U/6.3V_8
10U/6.3V_8
AD33
C14
AN21
AP24
VCC23
VTT0_23
VAXG13
GFX_VID[5]
GFXVR_VID_5
<40>
C237
C237
10U/6.3V_8
10U/6.3V_8
AD32
C13
AN19
AN24
GFXVR_VID_6
<40>
VCC24
VTT0_24
VAXG14
GFX_VID[6]
C648
C648
10U/6.3V_8
10U/6.3V_8
AD31
C12
AN18
VCC25
VTT0_25
VAXG15
C145
C145
10U/6.3V_8
10U/6.3V_8
AD30
C11
Please note that +VCC_GFX_CORE
should be 1.05V in Auburndale
AN16
GFX_VR_EN
Rc
R426
R426
*4.7K_4
*4.7K_4
VCC26
VTT0_26
VAXG16
C203
C203
10U/6.3V_8
10U/6.3V_8
AD29
B14
AM21
AR25
VCC27
VTT0_27
VAXG17
GFX_VR_EN
GFXVR_EN <40>
GFXVR_DPRSLPVR
C646
C646
10U/6.3V_8
10U/6.3V_8
Rd
R427
R427
*0_4
*0_4
AD28
B12
AM19
AT25
VCC28
VTT0_28
VAXG18
GFX_DPRSLPVR
<40>
C234
C234
10U/6.3V_8
10U/6.3V_8
Re
R196
R196
*0_4
*0_4
AD27
A14
AM18
AM24
GFXVR_IMON
<40>
VCC29
VTT0_29
VAXG19
GFX_IMON
C233
C233
0.1U/10V_4
0.1U/10V_4
Rf
R195
R195
*1K/J_4
*1K/J_4
AD26
A13
AM16
+VGACORE_IGPU
VCC30
VTT0_30
VAXG20
for S3 power reduction
C227
C227
0.1U/10V_4
0.1U/10V_4
AC35
A12
C641
C641
*22U/6.3V_8S
*22U/6.3V_8S
AL21
VCC31
VTT0_31
VAXG21
+1.5VSUS
AC34
A11
C642
C642
*22U/6.3V_8S
*22U/6.3V_8S
AL19
VCC32
VTT0_32
VAXG22
C154
C154
2
1
*0.047U/10V
*0.047U/10V
AC33
C644
C644
*10U/6.3V_8
*10U/6.3V_8
AL18
2A
VCC33
VAXG23
C153
C153
*0.047U/10V
*0.047U/10V
C643
C643
*10U/6.3V_8
*10U/6.3V_8
2
1
AC32
AL16
VCC34
VAXG24
C152
C152
*0.047U/10V
*0.047U/10V
Q9
AON6718L
Q9
AON6718L
2
1
AC31
AK21
AJ1
VCC35
VAXG25
VDDQ1
AC30
AF10
AK19
AF1
C92
C92
1U/6.3V_4
1U/6.3V_4
SI modify
R100
R100
+1.05V_VTT
VCC36
VTT0_33
VAXG26
VDDQ2
AC29
AE10
AK18
AE7
C121
C121
1U/6.3V_4
1U/6.3V_4
D
S
D
S
VCC37
VTT0_34
VAXG27
VDDQ3
AC28
AC10
C102
C102
22U/6.3V_8S
22U/6.3V_8S
AK16
AE4
C133
C133
1U/6.3V_4
1U/6.3V_4
G
G
VCC38
VTT0_35
VAXG28
VDDQ4
C126
C126
22U/6.3V_8S
22U/6.3V_8S
C108
C108
1U/6.3V_4
1U/6.3V_4
B
AC27
AB10
AJ21
AC1
4
B
VCC39
VTT0_36
VAXG29
VDDQ5
<38>
MAIND
C82
C82
1U/6.3V_4
1U/6.3V_4
AC26
Y10
AJ19
AB7
VCC40
VTT0_37
VAXG30
VDDQ6
C86
C86
22U/6.3V_8S
22U/6.3V_8S
*0/F_2512
*0/F_2512
AA35
W10
AJ18
AB4
VCC41
VTT0_38
VAXG31
VDDQ7
AA34
U10
VTT Rail Values are
Auburndal VTT=1.05V
Clarksfield VTT=1.1V
DIS
UMA
AJ16
Y1
C77
C77
22U/6.3V_8S
22U/6.3V_8S
VCC42
VTT0_39
VAXG32
VDDQ8
AA33
T10
AH21
W7
VCC43
VTT0_40
VAXG33
VDDQ9
<12,38>
MAINON_G
AA32
J12
Ra
0 ohm
NA
AH19
W4
C80
C80
*330U/2V_7343
*330U/2V_7343
VCC44
VTT0_41
VAXG34
VDDQ10
AA31
J11
AH18
U1
VCC45
VTT0_42
VAXG35
VDDQ11
AA30
J16
AH16
T7
VCC46
VTT0_43
VAXG36
VDDQ12
Ra
AA29
J15
T4
0.1U/10V_4
0.1U/10V_4
C182
C182
1
3
VCC47
VTT0_44
VDDQ13
AA28
R383
R383
0_8
0_8
P1
R136
R136
220/F_4
220/F_4
VCC48
VDDQ14
AA27
N7
0.1U/10V_4
0.1U/10V_4
C142
C142
VCC49
VDDQ15
AA26
AN33
N4
Q10
Q10
2N7002E
2N7002E
VCC50
PSI#
H_PSI#
<34>
VDDQ16
+1.5VSUS
0.1U/10V_4
0.1U/10V_4
C261
C261
Y35
L1
VCC51
VDDQ17
Y34
J24
H1
+1.05V_VTT
VCC52
VTT1_45
VDDQ18
C104
C104
22U/6.3V_8S
22U/6.3V_8S
0.1U/10V_4
0.1U/10V_4
C189
C189
+1.5VSUS_L
Y33
AK35
J23
CPU_VID0
<34>
VCC53
VID[0]
VTT1_46
Y32
AK33
C600
C600
22U/6.3V_8S
22U/6.3V_8S
H25
CPU_VID1
<34>
VCC54
VID[1]
VTT1_47
Y31
AK34
VCC55
VID[2]
CPU_VID2
<34>
for S3 power reduction
Y30
AL35
VCC56
VID[3]
CPU_VID3
<34>
Y29
AL33
P10
VCC57
VID[4]
CPU_VID4
<34>
VTT0_59
+1.05V_VTT
C612
C612
10U/6.3V_8
10U/6.3V_8
Y28
AM33
K26
N10
CPU_VID5
<34>
+1.05V_VTT
VCC58
VID[5]
VTT1_48
VTT0_60
Y27
AM35
C539
C539
22U/6.3V_8S
22U/6.3V_8S
J27
L10
C620
C620
10U/6.3V_8
10U/6.3V_8
CPU_VID6
<34>
VCC59
VID[6]
VTT1_49
VTT0_61
Y26
AM34
C543
C543
22U/6.3V_8S
22U/6.3V_8S
J26
K10
C599
C599
22U/6.3V_8S
22U/6.3V_8S
DPRSLPVR
<34>
VCC60
PROC_DPRSLPVR
VTT1_50
VTT0_62
V35
C544
C544
22U/6.3V_8S
22U/6.3V_8S
J25
J22
C598
C598
22U/6.3V_8S
22U/6.3V_8S
VCC61
VTT1_51
VTT1_63
C103
C103
22U/6.3V_8S
22U/6.3V_8S
V34
H27
J20
VCC62
VTT1_52
VTT1_64
V33
G28
J18
VCC63
VTT1_53
VTT1_65
SI modify
V32
G15
G27
H21
VCC64
VTT_SELECT
VTT1_54
VTT1_66
V31
G26
H20
VCC65
VTT1_55
VTT1_67
V30
H_VTTVID1=Low, 1.1V
H_VTTVID1=High, 1.05V
F26
H19
VCC66
VTT1_56
VTT1_68
V29
E26
VCC67
VTT1_57
V28
E25
VCC68
VTT1_58
C
C
V27
L26
+1.8V
VCC69
VCCPLL1
V26
L27
C110
C110
22U/6.3V_8S
22U/6.3V_8S
VCC70
VCCPLL2
U35
M26
C258
C258
4.7U/6.3V_6
4.7U/6.3V_6
VCC71
VCCPLL3
U34
C111
C111
2.2U/6.3V_6
2.2U/6.3V_6
VCC72
U33
AN35
C263
C263
1U/6.3V_4
1U/6.3V_4
VCC73
ISENSE
I_MON
<34>
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
C602
C602
1U/6.3V_4
1U/6.3V_4
U32
VCC74
U31
B15
VTT_SENSE
<35>
VCC75
VTT_SENSE
U30
A15
VSS_SENSE_VTT
<35>
VCC76
VSS_SENSE_VTT
U29
VCC77
U28
CPU_VID0
R406
R406
1K/J_4
1K/J_4
VCC78
+1.05V_VTT
R389
R389
100/F_4
100/F_4
R398
R398
*1K/J_4
*1K/J_4
U27
VCC79
+VCORE
+VCORE
CPU_VID1
R405
R405
1K/J_4
1K/J_4
U26
AJ34
VCCSENSE
<34>
VCC80
VCC_SENSE
R397
R397
*1K/J_4
*1K/J_4
R35
AJ35
VSSSENSE
<34>
VCC81
VSS_SENSE
R34
R393
R393
100/F_4
100/F_4
CPU_VID2
R409
R409
1K/J_4
1K/J_4
VCC82
R33
R411
R411
*1K/J_4
*1K/J_4
VCC83
R32
CPU_VID3
CPU_VID4
R410
R410
*1K/J_4
*1K/J_4
VCC84
R412
R412
1K/J_4
1K/J_4
R31
VCC85
R413
R413
*1K/J_4
*1K/J_4
R30
VCC86
R29
R415
R415
1K/J_4
1K/J_4
VCC87
R28
CPU_VID5
R421
R421
1K/J_4
1K/J_4
VCC88
R27
R418
R418
*1K/J_4
*1K/J_4
VCC89
CPU_VID6
R414
R414
*1K/J_4
*1K/J_4
R26
VCC90
R416
R416
1K/J_4
1K/J_4
P35
VCC91
DPRSLPVR
R429
R429
1K/J_4
1K/J_4
P34
VCC92
P33
R428
R428
*1K/J_4
*1K/J_4
VCC93
P32
H_PSI#
R422
R422
*1K/J_4
*1K/J_4
VCC94
P31
R419
R419
1K/J_4
1K/J_4
VCC95
P30
VCC96
P29
VCC97
HFM_VID : Max 1.4V
LFM_VID : Min 0.65V
D
P28
D
VCC98
P27
VCC99
P26
VCC100
IC,AUB_CFD_rPGA,R1P0
IC,AUB_CFD_rPGA,R1P0
PROJECT :AX1
PROJECT :AX1
PROJECT :AX1
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
<34>
+VCORE
<3,10,11,29,30,34,35,40>
+1.05V_VTT
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
<3,12,13,37,38>
+1.5VSUS
Custom
Custom
Custom
PROCESSER 3/4(POWER)
PROCESSER 3/4(POWER)
PROCESSER 3/4(POWER)
1A
1A
1A
<11,33,38>
+1.8V
Date:
Date:
Date:
Thursday, December 03, 2009
Thursday, December 03, 2009
Thursday, December 03, 2009
Sheet
Sheet
Sheet
5
5
5
of
of
of
40
40
40
1
2
3
4
5
6
7
8
Plik z chomika:
marco.marc
Inne pliki z tego folderu:
Compaq n610c_v n620 service guide.pdf
(10195 KB)
6050a0066801-mb-a02 - hp6220.pdf
(1064 KB)
6050A2327701 - VILLEMONT VV10 - INTEL DIS HP COMPAQ CQ320 CQ321.pdf
(1030 KB)
510-511- 610 (UMA)-.pdf
(538 KB)
2008129131956425.pdf
(143 KB)
Inne foldery tego chomika:
• TV LCD service manual
• Wsady pamięci (dump memory) różne
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