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Philips Semiconductors
Objective specification
I 2 C-bus controlled PAL/NTSC TV
processor
TDA8366
FEATURES
·
Multistandard vision IF circuit (positive and
negative modulation)
·
Video identification circuit in the IF circuit which is
independent of the synchronization for stable On Screen
Display (OSD) under ‘no-signal’ conditions
·
Source selection with 2 Colour Video Blanking
Synchronization (CVBS) inputs and a Y/C (or extra
CVBS) input
GENERAL DESCRIPTION
The TDA8366 is an I 2 C-bus controlled PAL/NTSC TV
processor. The circuit has been designed for use with the
baseband chrominance delay line TDA4665 and for
DC-coupled vertical and East-West (EW) output stages.
The device can process both CVBS and Y/C input signals
and has a linear RGB-input with fast blanking.
The peaking circuit generates asymmetrical overshoots
(the amplitude of the ‘black’ overshoots is approximately
2 times higher as the one of the ‘white’ overshoots) and
contains a (defeatable) coring function.
The RGB control circuit contains a black-current stabilizer
circuit with internal clamp capacitors. The white point of the
picture tube is adjusted via the I 2 C-bus.
The deflection control circuit provides a drive pulse for the
horizontal output stage, a differential sawtooth current for
the vertical output stage and an East-West drive current for
the East-West output stage.These signals can be
manipulated for geometry correction of the picture.
The supply voltage for the IC is 8 V. The IC is available in
an SDIP package with 52 pins and in a QFP package with
64 pins (see Chapter “Ordering information”).
The pin numbers indicated in this document are
referenced to the SDIP52; SOT247-1 package; unless
otherwise indicated.
·
Output signals of the video switch circuit for the teletext
decoder and a Picture-In-Picture (PIP) processor
·
Integrated chrominance trap and bandpass filters
(automatically calibrated)
·
Integrated luminance delay line
·
Asymmetrical peaking in the luminance channel with a
(defeatable) noise coring function
·
PAL/NTSC colour decoder with automatic search
system
·
Easy interfacing with the TDA8395 (SECAM decoder)
for multistandard applications
·
RGB control circuit with black-current stabilization and
white point adjustment; to obtain a good grey scale
tracking the black-current ratio of the 3 guns depends on
the white point adjustment
·
Linear RGB inputs and fast blanking
·
Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
·
Vertical count-down circuit
·
Geometry correction by means of modulation of the
vertical and EW drive
·
I 2 C-bus control of various functions
·
Low dissipation (850 mW)
·
Small amount of peripheral components compared with
competition ICs
·
Only one adjustment (vision IF demodulator)
·
Y, U and V inputs and outputs.
January 1995
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Philips Semiconductors
Objective specification
I 2 C-bus controlled PAL/NTSC TV
processor
TDA8366
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
TDA8366
SDIP52
plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
TDA8366H
QFP64 (1)
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 ´ 20 ´ 2.8 mm
SOT319-2
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook”
(order number 9398 510 63011) are followed.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Supply
V P
supply voltage
-
8.0
-
V
I P
supply current
-
100
-
mA
Input voltages
V 46,47(rms)
video IF amplifier sensitivity (RMS value)
-
70
-
m
V
V 15(p-p)
external CVBS input (peak-to-peak value)
-
1.0
-
V
V 9(p-p)
S-VHS luminance input voltage (peak-to-peak value)
-
1.0
-
V
V 8(p-p)
S-VHS chroma input voltage (burst amplitude)
(peak-to-peak value)
-
0.3
-
V
V 21,22,23(p-p)
RGB inputs (peak-to-peak value)
-
0.7
-
V
Output signals
V o(p-p)
demodulated CVBS output (peak-to-peak value)
-
2.5
-
V
I 52
tuner AGC output current range
0
-
5
mA
V 36(p-p)
TXT output voltage (peak-to-peak value)
-
1.0
-
V
V 13(p-p)
PIP output voltage (peak-to-peak value)
-
1.0
-
V
V 28(p-p)
- (R - Y) output voltage (peak-to-peak value)
-
525
-
mV
V 27(p-p)
-
(B
-
Y) output voltage (peak-to-peak value)
-
675
-
mV
V 26
Y output voltage
-
450
-
mV
V 19,18,17(p-p)
RGB output signal amplitudes (peak-to-peak value)
-
2.0
-
V
I 38
horizontal output current
10
-
-
mA
I 44,45
vertical output current
1
-
-
mA
I 43
EW drive output current
0.5
-
-
mA
January 1995
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PH1LF
DEC DIG
DEC BG
FBI
PH2LF
V ( 8 V)
P2
SCO
V ( 8 V)
SCL
SDA
HOUT
10
35
5
6
41
7
3
40
39
37 38
AGCOUT
(TUNER)
52
51
AGC FOR IF
AND TUNER
TOP
I C-BUS
TRANSCEIVER
2
VCO
AND
CONTROL
2nd LOOP AND
HORIZONTAL
OUTPUT
43
ref
EW GEOMETRY
EWD
DEC AGC
POL
48
EHTO
VDR
47
CONTROL DACs
17 x 6 bits
2 x 4 bits
SYNC
SEPARATOR
AND 1st LOOP
HORIZONTAL/
VERTICAL
DIVIDER
44
IFIN2
IF AMPLIFIER
AND DEMODULATOR
VERTICAL
GEOMETRY
(pos)
46
45
IFIN1
IFDEM2
VDR (ne g)
2
49
VSC
POL
50
I ref
1
VIDEO
AMPLIFIER
TDA8366
VERTICAL
SYNC
SEPARATOR
BLACK
CURRENT
STABILIZER
16
IFDEM1
BLKIN
WHITE
POINT
AFC AND
SAMPLE AND HOLD
MUTE
ref
B R I CONTR
20
BCLIN
19
18
17
AFC
IDENT
DELAY
AND
PEAKING
RGB MATRIX
AND
OUTPUT
RO
GO
BO
FILTER
TUNING
VIDEO MUTE
TRAP
BANDPASS
VIDEO
IDENTIFICATION
SW
SW
SAT
HU E
G-Y MATRIX
AND
SAT CONTROL
RGB INPUT
AND
SWITCH
CVBS - SWITCH
S-VHS - SWITCH
PAL/NTSC
DECODER
12
42
4 11
15
8
9
13 36
14 31
34
33
32
28 27
30
29
26 25 21 22 23 24
MLA745 - 1
GND1 GND2
IFVO
CVBS
INT
DEC
FT
DET
RYO BYO
RYI
BYI
RI GI BI
CVBS EXT
PIPO
CVBS/TXT
4.4
MHz
3.6
MHz
LUMIN
RGBIN
SOUND
TRAP
CHROMA
TDA4661
LUMOUT
CVBS/Y
SEC
ref
XTAL2 XTAL1
Fig.1 Block diagram (SDIP52; SOT247-1).
P1
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Philips Semiconductors
Objective specification
I 2 C-bus controlled PAL/NTSC TV
processor
TDA8366
PINNING
PIN
SYMBOL
DESCRIPTION
SDIP52
QFP64
IFDEM1
1
11
IF demodulator tuned circuit 1
IFDEM2
2
12
IF demodulator tuned circuit 2
DEC DIG
3
13
decoupling digital supply
IFVO
4
14
IF video output
SCL
5
16
serial clock input
SDA
6
17
serial data input/output
DEC BG
7
18
bandgap decoupling
CHROMA
8
20
chrominance input (S-VHS)
CVBS/Y
9
21
external CVBS/Y input
V P1
10
22
main supply voltage 1 (+8 V)
CVBS INT
11
29
internal CVBS input
GND1
12
25
ground 1
PIPO
13
27
picture-in-picture output
DEC FT
14
28
decoupling filter tuning
CVBS EXT
15
24
external CVBS input
BLKIN
16
30
black-current input
BO
17
31
blue output
GO
18
32
green output
RO
19
33
red output
BCLIN
20
35
beam current limiter input
RI
21
37
red input for insertion
GI
22
38
green input for insertion
BI
23
39
blue input for insertion
RGBIN
24
40
RGB insertion input
LUMIN
25
42
luminance input
LUMOUT
26
43
luminance output
BYO
27
44
(B
-
Y) signal output
RYO
28
45
(R - Y) signal output
BYI
29
46
(B
-
Y) signal input
RYI
30
47
(R - Y) signal input
SEC ref
31
48
SECAM reference output
XTAL1
32
49
3.58 MHz crystal connection
XTAL2
33
50
4.43/3.58 MHz crystal connection
DET
34
52
loop filter phase detector
V P2
35
54
horizontal oscillator supply voltage (+8 V)
CVBS/TXT
36
55
CVBS/TXT output
SCO
37
56
sandcastle output
HOUT
38
57
horizontal output
January 1995
5
11039372.029.png
Philips Semiconductors
Objective specification
I 2 C-bus controlled PAL/NTSC TV
processor
TDA8366
PIN
SYMBOL
DESCRIPTION
SDIP52
QFP64
FBI
39
58
flyback input
PH2LF
40
59
phase-2 filter
PH1LF
41
60
phase-1 filter
GND2
42
26
ground 2
EWD
43
63
east-west drive output
VDR (pos)
44
64
vertical drive 1 positive output
VDR (neg)
45
1
vertical drive 2 negative output
IFIN1
46
2
IF input 1
IFIN2
47
3
IF input 2
EHTO
48
4
EHT/overvoltage protection input
VSC
49
5
vertical sawtooth capacitor
I ref
50
6
reference current input
DEC AGC
51
7
AGC decoupling capacitor
AGCOUT
52
8
tuner AGC output
n.c.
-
9
not connected
n.c.
-
10
not connected
n.c.
-
15
not connected
n.c.
-
19
not connected
n.c.
-
34
not connected
n.c.
-
36
not connected
n.c.
-
41
not connected
n.c.
-
51
not connected
n.c.
-
53
not connected
V P3
-
23
supply voltage 3 (+8 V)
GND3
-
61
ground 3
GND4
-
62
ground 4
The pin numbers mentioned in the rest of this document are referenced to the SDIP52 (SOT247-1) package.
January 1995
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