TEA5170.PDF

TEA5170

SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT

. INTERNAL PWM SIGNAL GENERATOR

. POWER SUPPLY WIDE RANGE 4.5V – 14.5V

. WIDE FREQUENCY RANGE 250kHz

. MINIMUM OUTPUT PULSE WIDTH 500nS

. MAXIMUM PRESET DUTY CYCLE

. SYNCHRONIZATION WINDOW

. OUTPUT SWITCH

. UNDERVOLTAGE LOCKOUT

. FREQUENCY RANGE WITH SYNCHRONIZA-

TION 64kHz

DIP8

(Plastic Package)

ORDER CODE : TEA5170

DESCRIPTION

The TEA5170 is designed to work in the secondary

part of an off-line SMPS, sending pulses to the

slaved TEA2260/61 which are located on the pri-

mary side of the main transformer. An accurate

regulated voltage is obtained by duty cycle control.

The TEA5170 can be externally synchronized by

higher or lower frequency signal, then it could be

used in applications like TV set ones. For more

details, refer to application note AN408/0591.

PIN CONNECTIONS

SOFT-START CAPA CITOR

CSF

OSCILLATOR RESISTOR

SUPPLY VOLTAGE

OSCILLATOR CAPACITOR

POWER OUTPUT

OUT

VOLTAGE ERROR AMPLIFIER OUTPUT

VOLTAGE ERROR AMPLIFIER

INVERTING INPUT

GROUND

GND

September 1993

1/9

. SOFT START

. REFERENCE VOLTAGE 2V ± 5%

TEA5170

BLOCK DIAGRAM

Comparator

OSCILLATOR

LOGIC

(SYNCHRO)

POWER OUTPUT

STAGE

2.7V

SOFT START AND

DUTY CYCLE LIMITING

PWM

LOGIC

Csf

Error Amplifier

E-

PWM

x-1

Monitor

Eout

GND

V CC

P out

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V CC

Supply Voltage

T j

Operating Junction Temperature

150

T stg

Storage Temperature Range

– 40, + 150

° C

THERMAL DATA

Symbol

Parameter

Value

Unit

R th (j-a)

Junction-ambient Thermal Resistance

C/W

RECOMMANDED OPERATING CONDITIONS

Symbol

Parameter

Min. Typ. Max. Unit

V CC

Power Supply Voltage

Timing Resistor

180

Timing Capacitor

0.12

1.8

Fosc

Oscillator Frequency

250

kHz

Fsy

Synchro Frequency

kHz

T amb

Operating Ambient Temperature

– 20

VRT

Voltage on Pin RT (8)

Volt

VCT

Current on Pin CT (1)

100

I SOURCE

Output Current

2/9

TEA5170

ELECTRICAL CHARACTERISTICS (T A =25 o C, V CC = 12V, unless otherwise specified)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

OSCILLATOR

Free Period

RT = 100k

W ±

60.40 65.60 70.80

CT = 1.2nF

0%, Vcc = 12V

RT = 100k

W ±

29.18 31.70 34.22

CT = 560pF

0%, Vcc = 12V

F OSC

(T)

Frequency drift due to ambient

temperature variation from 0 o Cto70 o C

F OSC

RT = 100k

W ±

0.01

CT = 1.2nF

0%, Vcc = 12V

(

70 o C

F OSC

(

0 o C

)

70 o CxF OSC (

25 o C

)

F OSC

(V CC )

Frequency drift due to V CC variation

from 5V to 12V

F OSC (

RT = 100k

W ±

0.07

%/V

CT = 1.2nF

12V

F OSC

(

)

7V xF OSC ( 12V )

ERROR VOLTAGE AMPLIFIER (V CC = 12V)

Ibias

Input Bias Current

Ein = 2V

0.2

Gvol

Voltage Gain

Gain Bandwidth

MHz

Slew Rate

INTERNAL VOLTAGE REFERENCE

V REF

Voltage Reference

Using the voltage error

amplifier as a follower

1.9

2.1

V REF (V CC ) Line Regulation V REF (

12V

V REF

(

)

V CC = 5V to 12V

– 3

0.4

mV/V

V REF (T) V REF drift with temperature

V REF

T A =0

Cto70

0.2

mV/

(

70 o C

V REF ( 0 o C )

70 o C

T ON MIN

T ONMIN A

Minimum Duty Cycle

Ct = 1.2nF ± 0%

Rt = 100k W ± 0%

1.77 2.53 3.29

m s

T ONMIN B

Minimum Duty Cycle

Ct = 560pf

1.04 1.49 1.94

Rt = 100k

W ±

POWER OUTPUT STAGE

V POUTH

Output High Level

I load = 1mA

6.3

6.9

7.5

V POUTL

Output Low Level

I load = – 1mA

0.5

0.8

1.1

I SINK

Sink Current

V POUT = 3V

190

I SOURCE

Source Current

V POUT = 3V

110 190

SYNCHRONISATION

F trig Max

Maximum Synchro Frequency

kHz

V trig

Synchro Triggering Threshold

2.7

T trigp

Synchro Triggering Pulse Width

at VRT = 2.7Volt (fig 5)

800

Wtrig +

Positive Triggering Window

T trig + -

T O

CT = 1.2nF

T O

RT = 100k

W ±

Wtrig –

Negative Triggering Window

T O

T trig

CT = 1.2nF

T O

RT = 100k

W ±

SOFT START

I csf

*Csf Load Current

V csf = 1V

2.5

3.7

Donmax

Maximum Duty Cycle

V cs > 2.5V, V CC = 12V

CT = 1.2nf

RT = 100k

W ±

*Csf is a high impedance capacitor

3/9

TEA5170

ELECTRICAL CHARACTERISTICS (T A =25 o C, V CC = 12V, unless otherwise specified) (continued)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

V CC MONITOR

V START

Turn-on Threshold

3.60

4.40

V HYST

Hysteresis Voltage

100

V STOP

Turn-off Threshold

3.50

TOTAL DEVICE

I CC

Supply Current

RT = 100k

W ±

0%, CT = 1.2nf

No Load on Pin 3, V CC = 12V

GENERAL DESCRIPTION

The TEA5170 takes place in the secondary part of

an isolated off-line SMPS. During normal mode

operation, it sends pulses to the slave circuit lo-

cated in the primary side (TEA2164, TEA2260/61)

through a pulse transformer to achieve a very

precisely regulated voltage by duty cycle control.

The main blocs of the circuit are :

- an error voltage amplifier

- an RC oscillator

- an output stage

-aV CC monitor

- a voltage reference bloc

- a pulse width modulator

- two logic blocs

- a soft start and Duty cycle limiting bloc

ASYNCHRONIZED MODE (Figure 2)

The regulated voltage image is compared to 2V

vol-tage reference. The error voltage amplifier out-

put and the RC oscillator voltage ramp are applied

to the internal Pulse Width Modulator Inputs.

The PWM logic Output is connected to a logic bloc

which behaves like a RS latch, sets by the PWM

output and resets when Ct downloading occurs.

Finally, the push-pull output bloc delivers square

wave signal whom output leading edge occurs

during Ct uploading time, and output trailing edge

at Ct downloading time end. The duty cycle is

limited to 75% of oscillator period as maximum

value and to Ct downloading time/oscillator period

as minimum value (Figure 2).

Figure 2

PRINCIPLE OF OPERATION

The TEA5170 sends pulses continuously to the

slave circuit in order to insure a proper behaviour

of the primary side.

- According to this, the output duty cycle is varying

between D ON (min.) (0.05) and D ON (max.) (0.75) :

then even in case of open load, pulses are still

sent to the slave circuit.

OSCILLATOR RAMP

t max.

POWER OUTPUT

Figure 1 : Basic Concept

MASTER-SLAVE ARCHITECTURE

T2 = T on min.

T on max.

MASTER

CIRCUIT

SYNCHRONIZED MODE (see Figure 3)

The TEA5170 will enter the Synchronized Mode

when it receives one pulse through Rt during Ct

discharge.

At that time Ct charging current will be multiplied

by 0.75 and period will increase up to To x 1.26.

A pulse occuring during the synchro window, com-

mands the Ct downloading. If none, the TEA5170

will return to normal mode at the end of the period.

SLAVE

CIRCUIT

PWM

4/9

TEA5170

Figure 3

UNSYNCHRONIZED

MODE

SYNCH RONIZED MODE

UNSYNCHRONIZED

MODE

Vct

Vtsy

Vrt

Wtrig-

Wtrig+

Remark : In case of an application between

TEA5170 and TEA2164, to optimize the

synchronization windows of these

circuits, the following relations have to

be used : T m

Figure 4 : Triggering Schematic

V CC

T m

1.223

with T e : Free period of the TEA2164

oscillator, and T m : Free period of the

TEA5170 oscillator.

T SYNC

1.06

T e

from logic

BLOCK DESCRIPTION

The error voltage amplifier inverting-input and out-

put are accessible to use different feed-back net-

work and allowing parasitic filtering network. The

non-inverting input is internaly connected to 2V

reference voltage.

The RC oscillator is designed to work at high

frequency (up to 250kHz). R T sets the capacitor

charging current Io = 2/R T .

The capacitor C T is loaded from V 1

2.7V

Network

towards logic

2.7V

9 1V to V 2 =2V

Figure 5 : Typical Waveforms

C T R T

1.985 and then down loaded through

an integrated resistor R 2

during T1 =

9 1k W during T 2 = 1300 C T

The ramp is used to limit the duty cycle. Then the

maximum duty cycle is

Vct

T1 + T2 (

DONMAX

0.73 T1

)

The output level is V CC independant when V CC is

over 8V.

The V CC monitoring switches the circuit on when

V CC is over 4V and switches it off when under 3.8V.

This function insures a proper starting procedure

(made by the primary side circuit).

T trigP

Vrt

2.7V

SYNCHRONIZATION

(see Figures 4 and 5)

5/9

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