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Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9880-55
Logic level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
SYMBOL PARAMETER
MAX.
UNIT
level field-effect power transistor in a
plastic envelope suitable for surface
V
DS
Drain-source voltage
55
V
mounting. The device features very
I
D
Drain current
7.5
A
low on-state resistance and has
P
tot
Total power dissipation
1.8
W
integral zener diodes giving ESD
T
j
Junction temperature
150
˚C
protection. It is intended for use in
R
DS(ON)
Drain-source on-state
80
m
W
automotive and general purpose
resistance
V
GS
= 5 V
switching applications.
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
d
4
1
gate
2
drain
3
source
g
4
drain (tab)
1
2
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
-
55
V
V
DGR
Drain-gate voltage
R
GS
= 20 k
W
-
55
V
±
V
GS
Gate-source voltage
-
-
10
V
I
D
Drain current (DC)
T
sp
= 25 ˚C
-
7.5
A
I
D
Drain current (DC)
On PCB in Fig.2
-
3.5
A
T
amb
= 25 ˚C
I
D
Drain current (DC)
On PCB in Fig.2
-
2.2
A
T
amb
= 100 ˚C
I
DM
Drain current (pulse peak value)
T
sp
= 25 ˚C
-
40
A
P
tot
Total power dissipation
T
sp
= 25 ˚C
-
8.3
W
P
tot
Total power dissipation
On PCB in Fig.2
-
1.8
W
T
amb
= 25 ˚C
T
stg
, T
j
Storage & operating temperature
-
- 55
150
˚C
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge capacitor
Human body model
-
2
kV
voltage
(100 pF, 1.5 k
W
)
April 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9880-55
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-sp
From junction to solder point
Mounted on any PCB
12
15
K/W
R
th j-amb
From junction to ambient
Mounted on PCB of Fig.18
-
70
K/W
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown
V
GS
= 0 V; I
D
= 0.25 mA
55
-
-
V
voltage
T
j
= -55˚C
50
-
-
V
V
GS(TO)
Gate threshold voltage
V
DS
= V
GS
; I
D
= 1 mA
1.0
1.5
2.0
V
T
j
= 150˚C
0.6
-
-
V
T
j
= -55˚C
-
-
2.3
V
I
DSS
Zero gate voltage drain current V
DS
= 55 V; V
GS
= 0 V;
-
0.05
10
m
A
T
j
= 150˚C
-
-
100
m
A
I
GSS
Gate source leakage current
V
GS
=
±
5 V
-
0.02
1
m
A
T
j
= 150˚C
-
-
5
m
A
±
V
(BR)GSS
Gate source breakdown voltage I
G
=
±
1 mA
10
-
-
V
R
DS(ON)
Drain-source on-state
V
GS
= 5 V; I
D
= 5 A
-
65
80
m
W
resistance
T
j
= 150˚C
-
-
148
m
W
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
g
fs
Forward transconductance
V
DS
= 25 V; I
D
= 5 A; T
j
= 25˚C
4
8
-
S
C
iss
Input capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
500
650
pF
C
oss
Output capacitance
-
110
135
pF
C
rss
Feedback capacitance
-
60
85
pF
t
d on
Turn-on delay time
V
DD
= 30 V; I
D
= 7 A;
-
10
15
ns
t
r
Turn-on rise time
V
GS
= 5 V; R
G
= 10
W
;
-
30
50
ns
t
d off
Turn-off delay time
-
30
45
ns
t
f
Turn-off fall time
T
j
= 25˚C
-
30
40
ns
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= -55 to 175˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I
DR
Continuous reverse drain
T
sp
= 25˚C
-
-
7.5
A
current
I
DRM
Pulsed reverse drain current
T
sp
= 25˚C
-
-
40
A
V
SD
Diode forward voltage
I
F
= 5 A; V
GS
= 0 V
-
0.85
1.1
V
t
rr
Reverse recovery time
I
F
= 5 A; -dI
F
/dt = 100 A/
m
s;
-
38
-
ns
Q
rr
Reverse recovery charge
V
GS
= -10 V; V
R
= 30 V
-
0.2
-
m
C
April 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9880-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
W
DSS
Drain-source non-repetitive
I
D
= 2.5 A; V
DD
£
25 V;
-
-
30
mJ
unclamped inductive turn-off
V
GS
= 5 V; R
GS
= 50
W
; T
sp
= 25 ˚C
energy
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
100
ID/A
RDS(ON) = VDS/ID
tp =
1 us
10us
10
100 us
DC
1 ms
1
10ms
100ms
0
20
40
60
80
100 120 140
0.1
Tmb / C
1
10
VDS/V
100
Fig.1. Normalised power dissipation.
PD% = 100
×
P
D
/P
D 25 ˚C
= f(T
sp
)
Fig.3. Safe operating area. T
sp
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
100
Zth/ (K/W)
10
0.5
0.2
0.1
0.05
0.02
1
P
t
p
D =
T
0.1
T
t
0
20
40
60
80
100 120 140
0.01
1.0E-06
0.0001
0.01
1
100
Tmb / C
t/s
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 ˚C
= f(T
sp
); conditions: V
GS
³
5 V
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
April 1998
3
Rev 1.100
D
t
p
×
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9880-55
Logic level FET
40
VGS/V =
10
15
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
ID/A
7
6
14
gfs/S
13
30
12
11
20
10
9
10
8
7
6
0
5
0
2
4
VDS/V
6
8
10
0
5
10
ID/A
15
20
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
115
RDS(ON)/mOhm
2.5
a
BUK98XX-55
Rds(on) normalised to 25degC
110
105
4.2
4
2
4.4
4.6
4.8
100
95
5
1.5
90
85
1
80
75
0.5
70
-100
-50
0
50
100
150
200
5
10
15
20
25
ID/A
Tmb / degC
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 5 A; V
GS
= 5 V
20
2.5
VGS(TO) / V
BUK98xx-55
ID/A
max.
15
2
typ.
1.5
10
min.
1
5
0.5
Tj/C =
150
25
0
-100
-50
0
50
100
150
200
0
1
2
3
4
5
VGS/V
Tj / C
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
April 1998
4
Rev 1.100
0
Philips Semiconductors
Product specification
TrenchMOS
Ô
transistor
BUK9880-55
Logic level FET
1E-01
Sub-Threshold Conduction
40
IF/A
1E-02
30
Tj/V =
150
25
2%
typ
98%
1E-03
20
1E-04
10
1E-05
1E-05
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
2.5
3
VSDS/V
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
1
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
.9
.8
.7
.6
.5
.4
Ciss
.3
.2
.1
Coss
Crss
0
20
40
60
80
100
120
140
0.01
0.1
1
10
100
VDS/V
Tmb / C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
sp
); conditions: I
D
= 2.5 A
6
VDS/V
+
VDD
5
L
VDS = 14V
4
VDS
-
VDS = 44V
VGS
3
-ID/10
0
2
0
T.U.T.
RGS
R 01
1
shunt
0
0
2
4
6
8
10
12
QG/nC
Fig.16. Avalanche energy test circuit.
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 7 A; parameter V
DS
W
DSS
=
0.5
×
LI
2
×
BV
DSS
/(
BV
DSS
-
V
DD
)
April 1998
5
Rev 1.100
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