AD1881A.pdf

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AC’97 SoundMAX ® Codec
AD1881A
AC’97 2.1 FEATURES
Variable Sample Rate
True Line-Level Output
Supports Secondary Codec Modes
AC’97 FEATURES
Designed for AC’97 Analog I/O Component
48-Lead LQFP Package
Multibit Converter Architecture for Improved
S/N Ratio Greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Four Analog Line-Level Stereo Inputs for Connection
from LINE, CD, VIDEO, and AUX
Two Analog Line-Level Mono Inputs for Speakerphone
and PC BEEP
Mono MIC Input Switchable from Two External
Sources
High Quality CD Input with Ground Sense
Stereo Line-Level Output
Mono Output for Speakerphone or Internal Speaker
Power Management Support
ENHANCED FEATURES
Mobile Low Power Mixer Mode
Digital Audio Mixer Mode
Full Duplex Variable 8 kHz to 48 kHz Sampling Rate
with 1 Hz Resolution
PHAT™ Stereo 3D Stereo Enhancement
Split Power Supplies (3.3 V Digital/5 V Analog)
Extended 6-Bit Master Volume Control
Audio Amp Power-Down Signal
FUNCTIONAL BLOCK DIAGRAM
CS0
CS1
EAPD
MODE
AD1881A
MODE/SYNCHRONIZER
MIC1
MIC2
0dB/
20dB
LINE_IN
AUX
PGA
16-BIT
A/D
CONVERTER
CD
VIDEO
PGA
16-BIT
A/D
CONVERTER
RESET
PHONE_IN
SYNC
MONO_OUT
MV
SAMPLE
RATE
GENERATORS
G
A
M
G
A
M
G
A
M
G
A
M
G
A
M
G
A
M
BIT_CLK
LNLVL_OUT_L
SDATA_OUT
POP
G
A
M
16-BIT
D/A
CONVERTER
LINE_OUT_L
MV
PHAT
STEREO
SDATA_IN
NC
D
A
M
LINE_OUT_R
MV
PHAT
STEREO
NC
G
A
M
16-BIT
D/A
CONVERTER
POP
LNLVL_OUT_R
A
M
G = GAIN
A = ATTENUATE
M = MUTE
MV = MASTER VOLUME
NC = NO CONNECT
PC_BEEP
OSCILLATORS
XTL_OUT XTL_IN
SoundMAX is a registered trademark and PHAT is a trademark of Analog Device, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
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AD1881A–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
DAC Test Conditions
Calibrated
–3 dB Attenuation Relative to Full-Scale
Input 0 dB
10 k
25
C
Digital Supply (V DD )
3.3
V
Analog Supply (V CC )
5.0
V
Sample Rate (F S )
48
kHz
Input Signal
1008
Hz
Output Load
ADC Test Conditions
Calibrated
0 dB Gain
Input –3.0 dB Relative to Full-Scale
Ω
ANALOG INPUT
Parameter
Min
Typ
Max
Unit
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP
1
V rms
2.83
V p-p
MIC with +20 dB Gain (M20 = 1)
0.1
V rms
0.283
V p-p
MIC with 0 dB Gain (M20 = 0)
1
V rms
2.83
V p-p
Input Impedance *
20
kΩ
Input Capacitance *
5
7.5
pF
MASTER VOLUME
Parameter
Min
Typ
Max
Unit
Step Size (0 dB to –94.5 dB); LINE_OUT_L, LINE_OUT_R
1.5
dB
Output Attenuation Range Span *
–94.5
dB
Step Size (0 dB to –46.5 dB); MONO_OUT
1.5
dB
Output Attenuation Range Span *
–46.5
dB
Mute Attenuation of 0 dB Fundamental *
80
dB
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter
Min
Typ
Max
Unit
Step Size (0 dB to 22.5 dB)
1.5
dB
PGA Gain Range Span
22.5
dB
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Parameter
Min
Typ
Max
Unit
Signal-to-Noise Ratio (SNR)
CD to LINE_OUT
90
dB
Other to LINE_OUT
90
dB
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC
1.5
dB
Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC
–46.5
dB
Step Size (0 dB to –45 dB): (All Steps Tested) PC_BEEP
3.0
dB
Input Gain/Attenuation Range: PC_BEEP
–45
dB
* Guaranteed, not tested.
Specifications subject to change without notice.
–2–
REV. 0
Temperature
°
323060861.005.png
AD1881A
DIGITAL DECIMATION AND INTERPOLATION FILTERS *
Parameter
Min
Typ
Max
Unit
Passband
0
0.4 × F S
Hz
Passband Ripple
± 0.09
dB
Transition Band
0.4 × F S
0.6 × F S
Hz
Stopband
0.6 × F S
∞
Hz
Stopband Rejection
–74
dB
Group Delay
12/F S
sec
Group Delay Variation Over Passband
0.0
µs
ANALOG-TO-DIGITAL CONVERTERS
Parameter
Min
Typ
Max
Unit
Resolution
16
Bits
Total Harmonic Distortion (THD)
0.02
%
–74
dB
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted)
87
dB
Signal-to-Intermodulation Distortion * (CCIF Method)
85
dB
ADC Crosstalk *
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
–100
–90
dB
LINE_IN to Other
–90
–85
dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
± 10
%
Interchannel Gain Mismatch (Difference of Gain Errors)
± 0.5
dB
ADC Offset Error
± 10.5
mV
DIGITAL-TO-ANALOG CONVERTERS
Parameter
Min
Typ
Max
Unit
Resolution
16
Bits
Total Harmonic Distortion (THD) LINE_OUT, LNLVL_OUT
0.02
%
–74
dB
Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted)
90
dB
Signal-to-Intermodulation Distortion * (CCIF Method)
85
dB
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
± 10
%
Interchannel Gain Mismatch (Difference of Gain Errors)
± 0.7
dB
DAC Crosstalk * (Input L, Zero R, Measure R_OUT; Input R, Zero L,
–80
dB
Measure L_OUT)
Total Audible Out-of-Band Energy (Measured from 0.6 × F S to 20 kHz) *
–40
dB
ANALOG OUTPUT
Parameter
Min
Typ
Max
Unit
Full-Scale Output Voltage
1
V rms
(LINE_OUT, LNLVL_OUT)
2.83
V p-p
Output Impedance *
500
Ω
External Load Impedance *
10
kΩ
Output Capacitance *
15
pF
External Load Capacitance
100
pF
V REF
2.0
2.2
2.5
V
V REF_OUT
2.2
V
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
± 5
mV
* Guaranteed, not tested.
Specifications subject to change without notice.
REV. 0
–3–
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AD1881A–SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
High Level Input Voltage (V IH ): Digital Inputs
0.65 × DV DD
V
Low Level Input Voltage (V IL )
0.35 × DV DD
V
High Level Output Voltage (V OH ), I OH = –0.5 mA
0.9
×
DV DD
V
Low Level Output Voltage (V OL ), I OL = +0.5 mA
0.1 × DV DD
V
Input Leakage Current
–10
+10
µA
Output Leakage Current
–10
+10
A
POWER SUPPLY
Parameter
Min
Typ
Max
Unit
Power Supply Range – Analog
4.75
5.25
V
Power Supply Range – Digital (3.3 V)
3.0
3.6
V
Power Dissipation – 5 V/3.3 V
280
mW
Analog Supply Current – 5 V
40
mA
Digital Supply Current – 3.3 V
23
mA
Power Supply Rejection (100 mV p-p Signal @ 1 kHz) *
40
dB
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS *
Parameter
Min
Typ
Max
Unit
Input Clock Frequency
24.576
MHz
Recommended Clock Duty Cycle
45
50
55
%
POWER-DOWN MODE
DV DD (3.3 V)
AV DD (5 V)
Parameter
Set Bits
Typ
Typ
Unit
ADC
PR0
17
30
mA
DAC
PR1
17
26
mA
ADC and DAC
PR1, PR0
4
20
mA
ADC + DAC + Mixer (Analog CD On) LPMIX, PR1, PR0
4
12
mA
Mixer
PR2
20
18
mA
ADC + Mixer
PR2, PR0
17
12
mA
DAC + Mixer
PR2, PR1
17
8
mA
ADC + DAC + Mixer
PR2, PR1, PR0
4
2
mA
Analog CD Only (AC-Link On)
LPMIX, PR5, PR1, PR0
4
12
mA
Analog CD Only (AC-Link Off)
LPMIX, PR1, PR0, PR4, PR5
0
12
mA
Standby
PR5, PR4, PR3, PR2, PR1, PR0
0
0.1
mA
* Guaranteed, not tested.
Specifications subject to change without notice.
–4–
REV. 0
µ
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AD1881A
TIMING PARAMETERS 1 (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max Unit
RESET Active Low Pulsewidth
t RST_LOW
50
ns
RESET Inactive to BIT_CLK Startup Delay
t RST2CLK
833
µs
SYNC Active High Pulsewidth
t SYNC_HIGH
80
ns
SYNC Low Pulsewidth
t SYNC_LOW
19.5
µs
SYNC Inactive to BIT_CLK Startup Delay
t SYNC2CLK
162.8
ns
BIT_CLK Frequency
12.288
MHz
BIT_CLK Period
t CLK_PERIOD
81.4
ns
BIT_CLK Output Jitter 2
750
ps
BIT_CLK High Pulsewidth
t CLK_HIGH
36.62 40.69
44.76 ns
BIT_CLK Low Pulsewidth
t CLK_LOW
36.62 40.69
44.76 ns
SYNC Frequency
48.0
kHz
SYNC Period
t SYNC_PERIOD
20.8
µs
Setup to Falling Edge of BIT_CLK
t SETUP
5
2.5
ns
Hold from Falling Edge of BIT_CLK
t HOLD
5
ns
BIT_CLK Rise Time
t RISECLK
2
4
10
ns
BIT_CLK Fall Time
t FALLCLK
2
4
10
ns
SYNC Rise Time
t RISESYNC
2
4
10
ns
SYNC Fall Time
t FALLSYNC
2
4
10
ns
SDATA_IN Rise Time
t RISEDIN
2
4
10
ns
SDATA_IN Fall Time
t FALLDIN
2
4
10
ns
SDATA_OUT Rise Time
t RISEDOUT
2
4
10
ns
SDATA_OUT Fall Time
t FALLDOUT
2
4
10
ns
End of Slot 2 to BIT_CLK, SDATA_IN Low
t S2_PDOWN
0
10
ms
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
t SETUP2RST
15
ns
Rising Edge of RESET to HI-Z Delay (ATE Test Mode)
t OFF
25
ns
Propagation Delay
15
ns
RESET Rise Time
50
ns
NOTES
1 Guaranteed, not tested.
2 Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
REV. 0
–5–
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