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N-channel TrenchMOS(TM) transistor Logic level FET
Philips Semiconductors
Product specification
N-channel TrenchMOS
Ô
transistor
PHP55N03LT, PHB55N03LT
Logic level FET
PHD55N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
• ’Trench’ technology
d
V DSS = 25 V
• Very low on-state resistance
• Fast switching
I D = 55 A
• Low thermal resistance
• Logic level compatible
g
R DS(ON)
£
14 m
W
(V GS = 10 V)
R DS(ON)
£
18 m
W
(V GS = 5 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’ trench ’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP55N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB55N03LT is supplied in the SOT404 (D 2 PAK) surface mounting package.
The PHD55N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D 2 PAK)
SOT428 (DPAK)
PIN DESCRIPTION
tab
tab
tab
1
gate
2
drain 1
3
source
2
2
123
1
3
1
3
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V DSS
Drain-source voltage
T j = 25 ˚C to 175˚C
-
25
V
V DGR
Drain-gate voltage
T j = 25 ˚C to 175˚C; R GS = 20 k
W
-
25
V
V GS
Gate-source voltage (DC)
-
±
15
V
V GSM
Gate-source voltage (pulse T j
£
150˚C
-
±
20
V
peak value)
I D
Drain current (DC)
T mb = 25 ˚C
-
55
A
T mb = 100 ˚C
-
38
A
I DM
Drain current (pulse peak
T mb = 25 ˚C
-
220
A
value)
P tot
Total power dissipation
T mb = 25 ˚C
-
103
W
T j , T stg
Operating junction and
- 55
175
˚C
storage temperature
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.200
30094479.011.png 30094479.012.png
 
Philips Semiconductors
Product specification
N-channel TrenchMOS
Ô
transistor
PHP55N03LT, PHB55N03LT
Logic level FET
PHD55N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
R th j-mb
Thermal resistance junction
-
-
1.45 K/W
to mounting base
R th j-a
Thermal resistance junction SOT78 package, in free air
-
60
-
K/W
to ambient
SOT404 and SOT428 packages, pcb
-
50
-
K/W
mounted, minimum footprint
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
W DSS
Drain-source non-repetitive I D = 25 A; V DD
£
15 V;
-
60
mJ
unclamped inductive turn-off V GS = 5 V; R GS = 50
W
; T mb = 25 ˚C
energy
ELECTRICAL CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V (BR)DSS
Drain-source breakdown
V GS = 0 V; I D = 0.25 mA;
25
-
-
V
voltage
T j = -55˚C
22
-
-
V
V GS(TO)
Gate threshold voltage
V DS = V GS ; I D = 1 mA
1
1.5
2
V
T j = 175˚C
0.5
-
-
V
T j = -55˚C
-
-
2.3
V
R DS(ON)
Drain-source on-state
V GS = 10 V; I D = 25 A
-
11
14
m
W
resistance
V GS = 10 V; I D = 25 A (SOT428 package)
-
14
16
m
W
V GS = 5 V; I D = 25 A
-
15
18
m
W
V GS = 5 V; I D = 25 A; T j = 175˚C
-
-
34
m
W
g fs
Forward transconductance
V DS = 25 V; I D = 25 A
10
28
-
S
I GSS
Gate source leakage current V GS =
±
5 V; V DS = 0 V
-
10
100
nA
I DSS
Zero gate voltage drain
V DS = 25 V; V GS = 0 V;
-
0.05
10
m
A
current
T j = 175˚C
-
-
500
m
A
Q g(tot)
Total gate charge
I D = 55 A; V DD = 15 V; V GS = 5 V
-
20
-
nC
Q gs
Gate-source charge
-
8
-
nC
Q gd
Gate-drain (Miller) charge
-
9
-
nC
t d on
Turn-on delay time
V DD = 15 V; I D = 25 A;
-
7
15
ns
t r
Turn-on rise time
V GS = 10 V; R G = 5
W
-
56
80
ns
t d off
Turn-off delay time
Resistive load
-
57
80
ns
t f
Turn-off fall time
-
38
50
ns
L d
Internal drain inductance
Measured tab to centre of die
-
3.5
-
nH
L d
Internal drain inductance
Measured from drain lead to centre of die
-
4.5
-
nH
(SOT78 package only)
L s
Internal source inductance
Measured from source lead to source
-
7.5
-
nH
bond pad
C iss
Input capacitance
V GS = 0 V; V DS = 20 V; f = 1 MHz
-
1230
-
pF
C oss
Output capacitance
-
354
-
pF
C rss
Feedback capacitance
-
254
-
pF
October 1999
2
Rev 1.200
30094479.013.png 30094479.001.png
Philips Semiconductors
Product specification
N-channel TrenchMOS
Ô
transistor
PHP55N03LT, PHB55N03LT
Logic level FET
PHD55N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T j = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
I S
Continuous source current
-
-
55
A
(body diode)
I SM
Pulsed source current (body
-
-
220
A
diode)
V SD
Diode forward voltage
I F = 25 A; V GS = 0 V
-
0.9
1.2
V
I F = 55 A; V GS = 0 V
-
1.0
-
t rr
Reverse recovery time
I F = 20 A; -dI F /dt = 100 A/
m
s;
-
87
-
ns
Q rr
Reverse recovery charge
V GS = 0 V; V R = 25 V
-
0.1
-
m
C
Normalised Power Derating, PD (%)
1000
Peak Pulsed Drain Current, IDM (A)
100
90
80
RDS(on) = VDS/ ID
70
100
tp = 10 us
60
50
100 us
40
30
10
1 ms
10 ms
20
D.C.
100 ms
10
0
1
0
25
50
75
100
125
150
175
1
10
100
Mounting Base temperature, Tmb (C)
Drain-Source Voltage, VDS (V)
Fig.1. Normalised power dissipation.
PD% = 100
×
P D /P D 25 ˚C = f(T mb )
Fig.3. Safe operating area
I D & I DM = f(V DS ); I DM single pulse; parameter t p
Normalised Current Derating, ID (%)
10
Transient thermal impedance, Zth j-mb (K/W)
100
90
80
70
1
D = 0.5
60
0.2
0.1
50
40
0.1
0.05
0.02
P
tp
D = tp/T
30
20
10
single pulse
T
0
0.01
0
25
50
75
100
125
150
175
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Mounting Base temperature, Tmb (C)
Pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100
I D /I D 25 ˚C = f(T mb ); V GS
³
5 V
Fig.4. Transient thermal impedance.
Z th j-mb = f(t); parameter D = t p /T
October 1999
3
Rev 1.200
×
30094479.002.png 30094479.003.png
Philips Semiconductors
Product specification
N-channel TrenchMOS
Ô
transistor
PHP55N03LT, PHB55N03LT
Logic level FET
PHD55N03LT
50
Drain Current, ID (A)
30
Transconductance, gfs (S)
VGS = 10 V
5 V
4.5 V
Tj = 25 C
VDS > ID X RDS(ON)
45
25
40
175 C
Tj = 25 C
35
20
30
3 V
25
15
2.8 V
20
15
2.6 V
10
10
2.4 V
5
5
2.2 V
0
2 V
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
5
10
15
20
25
30
35
40
Drain-Source Voltage, VDS (V)
Drain current, ID (A)
Fig.5. Typical output characteristics, T j = 25 ˚C.
I D = f(V DS ); parameter V GS
Fig.8. Typical transconductance, T j = 25 ˚C.
g fs = f(I D ); conditions: V DS = 25 V
Drain-Source On Resistance, RDS(on) (Ohms)
2
Normalised On-state Resistance
0.1
1.9
2.2 V 2.4 V
2.6 V
2.8V
Tj = 25 C
1.8
0.09
1.7
1.6
0.08
1.5
3 V
1.4
0.07
1.3
1.2
0.06
1.1
1
0.05
0.9
0.04
0.8
0.7
0.6
0.03
0.5
5 V
VGS =4.5 V
0.02
0.4
0.3
0.01
0.2
10V
0.1
0
0
0
5
10
15
20
25
30
35
40
45
50
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Drain Current, ID (A)
Junction temperature, Tj (C)
Fig.6. Typical on-state resistance, T j = 25 ˚C.
R DS(ON) = f(I D ); parameter V GS
Fig.9. Normalised drain-source on-state resistance.
a = R DS(ON) /R DS(ON)25 ˚C = f(T j )
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
2.25
40
VDS > ID X RDS(ON)
2
35
maximum
1.75
30
1.5
25
typical
1.25
20
1
minimum
15
0.75
10
175 C
0.5
5
Tj = 25 C
0.25
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
I D = f(V GS ) ; conditions: V DS = 25 V; parameter T j
Fig.10. Gate threshold voltage.
V GS(TO) = f(T j ); conditions: I D = 1 mA; V DS = V GS
October 1999
4
Rev 1.200
30094479.004.png 30094479.005.png 30094479.006.png 30094479.007.png 30094479.008.png
Philips Semiconductors
Product specification
N-channel TrenchMOS
Ô
transistor
PHP55N03LT, PHB55N03LT
Logic level FET
PHD55N03LT
1.0E-01
Drain current, ID (A)
VDS = 5 V
Gate-source voltage, VGS (V)
15
14
ID = 55A
Tj = 25 C
VDD = 15 V
1.0E-02
13
12
11
1.0E-03
10
9
8
minimum
typical
maximum
7
1.0E-04
6
5
4
1.0E-05
3
2
1
0
1.0E-06
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
3
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
I D = f(V GS) ; conditions: T j = 25 ˚C; V DS = V GS
Fig.13. Typical turn-on gate-charge characteristics.
V GS = f(Q G ); parameter V DS
Source-Drain Diode Current, IF (A)
Capacitances, Ciss, Coss, Crss (pF)
50
10000
VGS = 0 V
45
40
35
30
175 C
Ciss
25
1000
20
Tj = 25 C
15
Coss
Crss
10
5
0
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, C iss , C oss , C rss .
C = f(V DS ); conditions: V GS = 0 V; f = 1 MHz
Fig.14. Typical reverse diode current.
I F = f(V SDS ); conditions: V GS = 0 V; parameter T j
October 1999
5
Rev 1.200
30094479.009.png 30094479.010.png

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