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Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
DESCRIPTION
The Electronic Ballast controller chip has been designed in a bipolar
process. It is housed in a 20-lead dual-in-line plastic package. The
control chip contains the equivalent of two (2) switched mode power
supply control circuits. The first SMPS controller is a DC-to-DC
converter operating in the discontinuous current conduction mode.
It is used as a PFC in the ballast system to provide a DC voltage
step-up function, good AC power factor, low AC current harmonic
distortion, and circuit protection against some types of AC voltage
transients. The PFC uses pulse width modulation to control the
power transfer with an external MOS power transistor. The second
SMPS circuit is a half-bridge oscillator circuit. It converts the DC
output voltage of the PFC into a high frequency AC voltage for
operating lamps. Power transfer in this circuit is controlled by
changing the switch frequency. The half-bridge controller circuit is
capable of driving two external high voltage MOS power transistors
and it has circuits to regulate the lamp current, limit the peak lamp
voltage, and protect the power switches during fault conditions. This
electronic ballast controller circuit has the capability of being used in
a dimming application.
PIN CONFIGURATION
N Package
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
DC
OUT
C
T
C
P
D
MAX
DC
OV
R
T
RXCX
PF
V
REF
I
PRIM
V
LAMP
14
C
RECT
LI2
LI
CSI
OUT
H
13
V
CC
12
OUT
P
11
GND
SL00524
Figure 1. Pin Configuration
•
Selectable variable frequency modes
•
Programmable pre-hit and ignition
FEATURES:
•
•
Lamp over-voltage protection
Complete PFC correction and dimming ballast control on one IC
•
PFC over-voltage protection for preventing over-shooting due to
load removal
•
Low line current distortion PFC
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
°
0 to +85
C
20-Pin Plastic Dual-In-Line Package (DIP)
NE5565N
SOT146-1
BLOCK DIAGRAM
RXCX
R
T
V
LAMP
6
5
4
V
CC
C
RECT
LI2
LI
7
8
9
3
D
MAX
2
C
P
CSI
10
C
T
1
GND
11
OUT
P
12
20
DC
OUT
13
V
CC
14
15
16
17
18
19
OUT
H
I
PRIM
V
REF
PF
OV
DC
SL00525
Figure 2. Block Diagram
1996 May 21
1
853-1835 16843
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
AC
LINE
FLUORESCENT LAMPS
HALF-BRIDGE
SQUARE WAVE
OSCILLATOR
POWER FACTOR
CORRECTION
CIRCUIT
AC
FILTER
DC
SUPPLY
13
17
12
10
11
19
18
14
6
15
V
CC
PF
OUT
P
CSI
GND
DC
OV
OUT
H
V
LAMP
I
PRIM
RXCX
V
REF
R
T
D
MAX
C
P
C
T
DC
OUT
C
RECT
LI
LI2
5
16
4
3
2
1
20
7
9
8
R
5
R
4
R
T
R
X
R
1
R
2
C
T
C
3
R
3
C
P
C
2
C
X
DIMMING
INPUT
C
1
SL00526
Figure 3. Typical Application: 2-Lamps Dimming Ballast
Voltage Regulator
The V
REF
output provides a regulated output voltage of 7.42V at the
V
REF
pin. This voltage is used as a reference as well as the power
supply of the control logic. It is based on a trimmed band gap
voltage reference circuit. The nominal V
CC
voltage for the control
chip is 12.7V. The V
REF
circuit requires a minimum of 9.3V before it
can produce regulated output. The V
REF
output voltage has an
absolute accuracy of
±
3.5% over the temperature range of 0
°
C to
85
°
C.
above the upper trip point, both PFC and half-bridge oscillator
circuits become operational. When the V
CC
falls below the lower
trip point of 10V, both PFC and half-bridge circuits are disabled.
Once the half-bridge oscillator turns off, it is not allowed to turn back
on until V
CC
exceeds the upper trip point and a minimum time delay,
set by external components at the D
MAX
pin, has passed.
Start up Ckt
The Low Half-bridge Voltage Lock-out Circuit senses the DC output
voltage of the PFC SMPS clrcuit. It is used to inhibit the lamp
ignition sequence or frequency sweep of the half-bridge oscillator
until the PFC output voltage has reached a pre-determined value.
This value is set by external components. The PFC voltage is
sensed by the over voltage input pin, OV. When this input exceeds
5/7 of V
REF
the frequency sweep is allowed to occur, thus beginning
the lamp ignition sequence.
The Over Voltage Protection Circuit prevents the PFC DC output
voltage from exceeding a pre-determined value. When the voltage
at the OV pin is greater than V
REF
the PFC buffer gate drive output
OUT
P
is turned off. This prevents any further increase in PFC DC
output voltage. The over voltage circuit only protects against an
over voltage or over shoot generated by the PFC itself. This may
occur during turn on when the SMPS is not loaded and the circuit is
under damped. Transient voltages from the AC line are not
suppressed by this circuit.
Lamp Voltage Regulator
Limits the maximum open circuit voltage across the lamp load during
the pre-heat, ignition and lamp removal conditions. During steady
state operation, the lamp voltage is governed by the arc voltage of
the lamps, not by the control circuit. The lamp voltage comparator is
used to sense when the voltage at the V
LAMP
pin exceeds V
REF
. At
the time this occurs, the lamp voltage has reached its maximum
allowed open circuit value and the circuit responds by producing a
rapid frequency increase which reduces the voltage at the Vlamp
pin. The RxCx time constant sets the frequency sweep time of the
start up circuit. The frequency sweep range has a rate of 2:1.
Low Supply Lock-out Protection
Senses the DC power supply voltage at the V
CC
pin to determine
when the PFC and half-bridge control circuits should turn on or off.
This protection circuit uses a Schmitt trigger with a voltage reference
to determine the upper and lower trip points of the power supply
voltage. As the power supply voltage rises from 0V to a value just
below the upper trip point of 11V, both the PFC and the half-bridge
control circuits are held in the off state. Once the V
CC
voltage rises
Capacitive Load Protection
Prevents failure of the half-bridge power transistors during lamp
removal. It does this by limiting the operation of the half-bridge
oscillator to frequencies above the resonant frequency of an
2
1996 May 21
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
external LC network driven by the bridge. At frequencies above
resonance the primary voltage of the half-bridge LC load network
leads the primary current in phase. The protection logic senses the
LC network current phase relative to the half-bridge gate drive
voltage to determine if a resonant condition exists. The Iprim input
voltage represents the primary current signal from the external LC
network. If the voltage at Iprim is more positive than -100mV when
the gate drive signal is high, then a fault condition exists and the
half-bridge oscillator frequency is swept high.
triggers the over current protection circuit this turns off the OUT
P
output and forces the external capacitor connected to D
MAX
to
discharge when an over current condition occurs in the PFC input
circuit. An over current condition is usually produced during the turn
on transient of the SMPS or when the AC line voltage has a power
interruption.
Power Factor Amplifier
Senses the phase and amplitude of a peak rectified AC line voltage
in order to modulate the duty cycle of the PFC power switch. This is
done to improve the sinusoidal wave shape of the AC line current.
The power factor input is provided by the PF input pin. The voltage
at this pin is 1V when the AC line voltage reaches its peak and 0V
when the AC voltage is at its 0V crossing.
Half-Bridge Oscillator
Is a triangle wave generator used to produce a square wave signal
for driving the half-bridge buffer circuit. The triangle wave appears
on the C
t
capacitor output pin. The oscillator frequency is governed
by the value of the resistor connected to the R
t
input and the value
of the C
t
capacitor.
DC Error Amplifier
Provides negative feedback control of the PFC DC output voltage.
The DC pin senses the DC output voltage of the PFC through an
external resistor voltage divider and filter network. The reference
voltage for the DC error amplifier is V
REF
. The output of the
amplifier is available at the DC out pin and an external capacitor is
connected to this pin in order to remove switching frequency noise
before its signal is applied to the pulse width modulator in the PWM
oscillator circuit.
Output Buffer Drive
Convert the low level logic signals from the half-bridge oscillator and
pulse width modulator into a 10V drive signal for the power switches.
The OUT
H
half-bridge buffer/drive circuit will drive an external level
shift scheme which will then be used to operate the half-bridge
power switches. The OUT
P
output may directly drive a power
MOSFET switch or an external level shift/power MOSFET
combination.
Lamp Current Rectifier
Is used to provide negative feedback control of the average lamp
current. An external lamp current transformer and load resistor are
used to convert the lamp current signal into a voltage. This voltage
is applied to the lamp current input pins, Li1 and Li2. The full wave
rectified output is provided at C
RECT
pin. External resistors and a
capacitor determine the gain and time constant of the circuit. A
differential error amplifier compares the voltage of C
RECT
to an
internal reference of 2/7 V
REF
and adjusts the half-bridge oscillator
frequency so that the error voltage is minimized. This forces the
average lamp current to be a constant.
Pulse Width Modulator
Generates a ramp voltage used to control the duty cycle of the PFC
SMPS. The frequency of the pulse width modulator is set by the
half-bridge oscillator. The ramp voltage appears at the C
P
output. It
is synchronized to the half-bridge oscillator so that the beginning of
the ramp occurs at the valley of the C
t
triangle waveform. When the
ramp voltage at C
P
exceeds the voltage at the DC out pin in the DC
amplifier, the capacitor connected to C
P
is discharged. The period
of the PFC gate drive pulse correspond to the C
P
ramp time. The
maximum duty cycle, soft start function, and half-bridge off time are
all controlled by the external capacitor and resistors connected to
the D
MAX
pin.
Dimming
Dimming input should be an extra current put into charging C
3
in
addition to the current from Pin 7. This creates the same condition
as higher voltage differential across Pins 8 and 9, hence, the IC
reacts as if there is too much power applied to the lamps.
Over Current Protection
An over current is sensed by an external resistor connected to the
current sense input pin, CSl. A voltage of minus 500mV at CSl
3
1996 May 21
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
PIN DESCRIPTIONS/ABSOLUTE MAXIMUM RATINGS
Pin #
Name
Function
Rating
Units
1
C
t
Half-Bridge oscillator capacitor
7
V
2
C
P
PWM Capacitor for power factor correction circuit
7
V
3
D
MAX
Max Duty Cycle, soft start, and time delay R/C input
7
V
4
R
t
Resistor for setting the half-bridge frequency
±
0.7V or 500
m
A
V/
m
A
5
RxCx
Start resistor and capacitor input for setting frequency sweep time
7
V
6
V
LAMP
Lamp voltage regulator input
14
V
7
C
RECT
Lamp current rectifier capacitor input/dimming control input
7
V
8
Li2
Lamp current differential inputs
±
1V to Li1, 7V or V
REF
-0.7V to GND
V
Lamp current differential inputs
±
1V to Li1, 7V or V
REF
-0.7V to GND
V
9
Li1
10
CSl
Current sense input for over-current protection
+0.5 V / -2V
V
11
GND
Ground
0
V
12
OUT
P
Gate drive output for the PFC
14
V
13
V
CC
Positive power supply voltage
14
V
14
OUT
H
Gate drive output for the half-bridge DMOS
14
V
15
I
PRIM
Primary current sense input
+1V / -1.5 V or
±
500
m
A
V/
m
A
16
V
REF
Regulated output voltage and reference
V
CC
V
17
PF
Power factor input
7
V
18
OV
0ver-voltage comparator input
14
V
19
DC
DC error amplifier input
12
V
20
DC
OUT
DC error amplifier output for connecting to external filter capacitor
7
V
DC ELECTRICAL CHARACTERISTICS
V
CC
= +12.7V, T
A
= 25
°
C; unless otherwise stated.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN
TYP
MAX
DC Error Amplifier
DC input clamp current
DC = 0V
-403
-690
-941
m
A
DC bias current
DC = V
REF
-1
m
A
DC error amp reference
7.05
7.42
7.79
V
DC output HIGH voltage
DC = 7V
5.4
6.6
V
Power Factor Amplifier
PF input current
PF = 1V
-14
m
A
PF transconductance
65
100
135
m
A/V
Start-up Circuit
RxCx input current
RxCx = 0.5V
-8
m
A
RxCx threshold
1.51
1.59
1.67
V
OV input current
OV = 5V
-8
m
A
OV threshold
7.05
7.42
7.79
V
HB lockout threshold
4.93
5.3
5.67
V
Oscillator
R
t
voltage
.7
V
C
t
HIGH current
RxCx=0V Rt=100
m
A
-160
-200
-240
m
A
C
t
LOW current
RxCx=6.5V Rt=100
m
A
-80
-100
-120
m
A
C
t
HIGH threshold
4.14
4.6
5.06
V
C
t
LOW threshold
2.23
2.48
2.73
V
PWM
C
P
HIGH threshold
3.66
4.07
4.48
V
C
P
-to-D
MAX
threshold
D
MAX
= 4V
2.97
3.3
3.63
V
C
P
-to-DC output threshold
DC = 4V
2.97
3.3
3.63
V
4
1996 May 21
Philips Semiconductors
Product specification
Electronic ballast controller circuit
NE5565
DC ELECTRICAL CHARACTERISTICS
(continued)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
MIN
TYP
MAX
PWM (cont.)
D
MAX
input current
D
MAX
= 0.5V
-1
m
A
D
MAX
threshold
0.95
1.06
1.17
V
Power Supply
I
SUPPLY
static
V
CC
= 12.7V
9
18
mA
V
CC
Supply voltage
9.3
14
V
V
REF
Reference voltage
TRIMMED VALUE
7.42
V
V
REF
tolerance
0 to 85
°
C
±
3.5
%
V
REF
load current
-5
mA
I
REF
short circuit current
V
REF
= 0V
-30
mA
Buffer
IPC = 40mA
1
OUT
P
/ OUT
H
LOW
OUT
P
/ OUT
H
LOW
IPC = 250mA PULSE
3
V
V
V
IPC = -40mA
10.2
OUT
P
/ OUT
H
HIGH
OUT
P
/ OUT
H
HIGH
IPC = -250mA PULSE
8.1
OUT
P
/ OUT
H
peak triangle wave current
Magnetizing
±
40
mA
OUT
P
/ OUT
H
pulse current
Gate capacitance current
±
250
mA
Low supply upper trip point
10.45
11.0
11.55
V
Low supply lower trip point
9.5
10.0
10.5
V
Lamp Voltage Regulator
V
LAMP
input current
V
LAMP
= 6.5V
-8
m
A
V
LAMP
threshold
7.05
7.42
7.79
V
Load Protection
I
PRIM
input current
I
PRIM
= 0V
-60
-100
-140
m
A
I
PRlM
negative threshold
-60
-100
-140
mV
Over-current Protection
CSI input current
CSI = -1V
-60
-100
-140
m
A
CSI threshold
-400
-500
-650
mV
Rectifier (RLi = RLi2 = 4k, R
3
= 20k; VRLi = Voltage input to RLi1; VRLi2 = 0V, Input to RLi2)
Li input current
VRLi1 = VRLi2 = 0V
-120
-200
-280
m
A
C
RECT
output offset
VRLi1 = VRLi2 = 0V
150
mV
C
RECT
HIGH output
VRLi1 =
±
0.5V
4.42
4.66
4.9
V
C
RECT
gain
V
RECT
/VRLi1
8.86
9.33
9.80
C
RECT
error amp reference
2.01
2.12
2.23
V
5
1996 May 21
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