NTEELECTRONICS-NTE21256-262-144BitDynamicRandomAccessMemory(DRAM).pdf

NTE21256

262,144–Bit Dynamic Random

Access Memory (DRAM)

Description:

The NTE21256 is a 262,144 word by 1–bit dynamic Random Access Memory. This 5V–only component

is fabricated with N–channel silicon gate technology.

Nine multiplexed address inputs permit the NTE21256 to be packaged in an industry standard

16–Lead DIP package. Features of this device include single power supply with

10% tolerance, on–

chip address, date registers which eliminate the need for interface registers, and fully TTL compatible

inputs and outputs, including clocks.

In addition to the usu al rea d, write, and read–modify–write cycles, the NTE21256 is capable of early

and late write cycles, RAS–only refresh, and hidden refresh. Common I/O capability is given by using

early write operation.

The NTE21256 also features page mode which allows high–speed random access of bits in the same

row.

Features:

262,144 x 1–Bit Organization

Single +5V Supply,

10% Tolerance

Low Power Dissipation:

–385mW active (Max)

–28mW standby (Max)

Access Time: 150ns

Cycle Time: 260ns

All Inputs and Outputs TTL Compatible

On–Chip Substrate Bias Generator

Three–State Data Output

Read, Write, Read–Modify–Write, RAS–Only–Refresh, Hidden Refresh

Common I/O Capability using “Early Write” Operation

Page Mode Read and Write, Read–Write

256 Refresh Cycles with 4ms Refresh Period

Absolute Maximum Ratings: (Note 1)

Operating Temperature Range, T opr

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

to +70

Storage Temperature Range, T stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

to +150

Voltage on any pin relative to V SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–1 to +7V

Power Dissipation, P D

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Out Current (Short Circuit)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

50mA

Functional Description:

Device Initialization

Since the NTE21256 is a dynamic RAM with a single +5V supply, no power sequencing is required.

For power–up, an initial pause of 200

s is necessary for the internal bias generator to establish the

proper substrate bias voltage. To in itializ e the nodes of the dynamic circuitry, a minimum of 8 active

cycles of the Row Address Strobe (RAS) has to be performed. This is also necessary after an ex-

tended inactive state of greater than 4ms.

Addressing (A0–A8)

For selecting one of the 262,144 memory cells, a total of 18 address bits are required. First 8 Row

Address bits are set u p on pins A0 through A8 and latched into the row address latches by the Row

Address Strobe (RAS). Then the 9 column address bits are set u p on p ins A0 through A8 and latched

into the column address latch es by the Colu mn Address Strobe (CA S). A ll input addresses must be

stable on the falling edges of RAS and CAS. It should be noted th at RA S is similar to a Chip Enable

in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select acti-

vating the column decoder and the input and output buffers.

Write Enable (WE)

The read or write mode is selected with the WE input. A logic high (V IH ) on WE dictates read

mode; logi c low (V IL ) dictate s writ e mode. The data input is disabled when read mode is selected.

When WE goes low prior to CAS, data output (DO) will remain in the high–impedance state for the

entire cycle permitting common I/O operation.

Data Input (DI)

Data is written during a write or read–modify–write cy cle. The falling edge of CA S or WE strobes data

into the on–c hip da ta latch. In an early write cycle, WE is brought low prior to CAS and the data is

strobed in by CAS with setup and hold times referenced to this signal.

Data Output (DO)

The output is three–state TTL compatible with a fan–out of two standard TT L loa ds. Data Out has

the same polarity as Data In. The output is in a high impedance state until C AS is brought low. In

a read cycle or read–write cycle, the outp ut is valid after t RAC from transition of RAS when t RCD (Min)

is satisfied, or after t CAC from transition of CAS when the transition occurs after t RCD (Max). In an early

write cycle, the output is always in the high impedance state. In a delay ed write or read–modify–write

cycle, the output will follow the sequence for the read cycle. With CAS going high the output returns

to the high impedance state within t OFF .

Hidd en Refresh

RAS–only refresh cycle may take place while maintaining vali d outp ut data. This feature is referred

to as Hidden Refresh. Hidden Refresh is performed by holding CAS at V IL of a previous memory read

cycle.

Refresh Cycle

A refresh operation must be perfo rmed at least every 4ms to retain data. Since the output buffer is

in the high impedance state unless CAS is applied, the RAS–only refresh seque nce av oids any signal

during refresh. Strobing eac h of th e 256 row addresses (A0 through A7) with RAS, causes all bits

in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve

power.

Page Mode

Page–mode operation allows effectively faster memory access by maintaining the row address and

strobing random column addresses onto the chip. Thus, the time necessary to setup and strobe se-

quential row addresses for the same page is no longer required. The max imu m number of columns

that can be addressed in sequence is determined by t RAS , the maximum RAS low pulse width.

DC Characteristics: (T A = 0

to +70

C, V SS = 0V, V CC = +5V

10% unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input High Voltage (All Inputs)

V IH

Notes 2, Note3

2.4

–

V CC +1

Input Low Voltage (All Inputs)

V IL

Notes 2, Note3

–1.0

–

0.8

Output High Voltage

V OH

Note 4

2.4

–

Output Low Voltage

V OL

Note 5

–

0.4

Average V CC Supply Current

I CC1

t RC = 260ns, Note 6

–

Standby V CC Supply Current

I CC2

Note 7

–

Av erag e V CC Supply Current during

RAS–only refresh cycles

I CC3

Note 6

–

Average V CC supply Current during

Page Mode

I CC4

Note 6

–

Input Leakage Current (Any Input)

I I (L)

–

Output Leakage Current

I O (L)

CAS at Logic 1, 0

V out

5.5

–

Supply Voltage

V CC

Note 2

4.5

–

5.5

V SS

–

Note 2. All voltages referenced to V SS .

Note 3. Overshooting and undershooting on input levels of +6.5V or –2V for a period 0f 30ns Max.

will influence function and reliability of the device.

Note 4. I OH = 4mA and 100pf load.

Note 5. I OL = 4mA and 100pf load.

Note 6. I CC depends on frequency of operation. Maximum current is measured at the fastest cycle

rate.

Note 7. RAS and CAS are both at V IH .

Capacitance: (Note 6)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Capacitance (A0–A8, DI)

C I1

–

Input Capacitance (RAS, CAS, WE)

C I2

–

Output Capacitance (DO, CAS = V IH to disable output)

C O

–

Note 6. Effective capacitance calculated from the equation:

C =

with

V = 3V or measured with Boonton meter.

AC Test Conditions:

Input Pulse Levels

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise and Fall Times

0 to 3.0V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Reference Levels

5ns between 0.8 and 2.4V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Levels

0.8 to 2.4V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0.4 to 2.4V

Output Load

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

equivelent to 2 standard TTL loads and 100pf

AC Characteristics: (T A = 0

to +70

C, V CC = 5V

10%, Note 9, Note 10, Note 11 unless

otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Random Read or Write Cycle Time

t RC

Note 12

260

–

Read–Modify–Write Cycle Time

t RWC

Note 12

310

–

Access Time from RAS

t RAC

Notes 13, Note 14

–

150

Access Time from CAS

t CAC

Notes 13, Note 15

–

10 4

RAS Pulse Width

t RAS

150

–

CAS Pulse Width

t CAS

–

Refresh Period

t REF

–

RAS Precharge Time

t RP

100

–

CAS to RAS Precharge Time

t CRP

–

RAS to CAS Delay Time

t RCD

Note 16

–

RAS Hold Time

t RSH

–

CAS Hold Time

t CSH

150

–

Row Address Setup Time

t ASR

–

Row Address Hold Time

t RAH

–

Column Address Setup Time

t ASC

–

Column Address Hold Time

t CAH

–

Column Address Hold Time referenced to RAS

t AR

Note 17

105

–

Transition Time (Rise and Fall)

t T

Note 9

–

Read Command Setup Time

t RCS

–

Read Command Hold Time referenced to CAS

t RCH

Note 18

–

Read Command Hold Time referenced to RAS

t RRH

Note 18

–

Output Buffer Turn–Off Delay

t OFF

Note 19

–

Note 9. V IH and V IL are reference levels to measure timing of input signals. Also, transition times

are measured between V IH and V IL .

Note10. An initial pause of 200

s is required after power–up followed by a minimum of eight initialization

cycles prior to normal operation.

Note 11. The time parameters specified here are valid for a transition time of t T = 5ns for the input signals

Note12. The specification for t RC (Min), t RWC (Min), and page–mode cycle time (t PC ) are only used

to indicate cycle time at which proper operation over full temperature range

C) is assured.

Note13. Measured with a load equivalent to two TTL loads and 100pf.

Note14. Assumes that t RCD

T A

+70

t RCD (Max). If t RCD is greater than the maximum recommended value

shown in this table, t RAC will increase by the amount that t RCD exceeds the value shown.

Note15. Assumes that t RCD

t RCD (Max).

Note16. Operation within the t RCD (Max) limit ensures that t RAC (Max) can be met. t RCD (Max) is spe-

cified as a reference point only. If t RCD is greater than the specified t RCD (Max) limit, then

access time is controlled exclusively by t CAC .

Note17. t RCD + t CAH

t AR Min, t RCD + t DH

t DHR Min, t RCD + t WCH

t WCR Min.

Note18. Either t RRH or t RCH must be satisfied for a read cycle.

Note19. t OFF (Max) defines the time at which the output achieves the open circuit condition and is not

referenced to output voltage levels.

AC Characteristics (Cont’d):

(T A = 0

to +70

C, V CC = 5V

10%, Note 9, Note 10, Note 11

unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Write Command Setup Time

t WCS

Note 20

–

Write Command Hold Time

t WCH

–

Write Command Hold Time referenced to RAS

t WCR

Note 17

120

–

Write Command Pulse Width

t WP

–

Write Command to RAS Lead Time

t RWL

–

Write Command to CAS Lead Time

t CWL

–

Data in Setup Time

t DS

Note 21

–

Data in Hold Time

t DH

Note 21

–

Data in Hold Time referenced to RAS

t DHR

Note 17

120

–

CAS to WE Delay

t CWD

Note 20

–

RAS to WE Delay

t RWD

Note 20

150

–

RMW Cycle RAS Pulse Width

t RRW

200

–

RMW Cycle CAS Pulse Width

t CRW

125

–

Page Mode Cycle Time

t PC

Note 12

145

–

Page Mode Read–Write Cycle Time

t PRWC

190

–

Page Mode CAS Precharge Time

t CP

–

Note 9. V IH and V IL are reference levels to measure timing of input signals. Also, transition times

are measured between V IH and V IL .

Note10. An initial pause of 200

s is required after power–up followed by a minimum of eight initialization

cycles prior to normal operation.

Note 11. The time parameters specified here are valid for a transition time of t T = 5ns for the input signals

Note12. The specification for t RC (Min), t RWC (Min), and page–mode cycle time (t PC ) are only used

to indicate cycle time at which proper operation over full temperature range

T A

+70

C) is assured.

Note17. t RCD + t CAH

t WCR Min.

Note20. t WCS , t CWD , and t RWC are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only: If t WCS

t AR Min, t RCD + t DH

t DHR Min, t RCD + t WCH

t WCS (Min), the cycle is an early write cycle

and the Data Out will remain open circuit (high impedance) throughout the entire cycle; if

t CWD

t RWD (Min) the cycle is a read–write cycle and the Data Out

will contain data read from the selected cell. If neither of the above sets of conditions is satis-

fied, the condition of the Data Out (at access ti me) is indeterminate.

Note21. t DS and t DH a re referenced to the leading edge of CAS in early write cycles, and to the leading

edge of WE in delayed write of read–modify–write cycles.

t CWD (Min) and t RWD

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