54ABT244.pdf

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July 1998
54ABT244
Octal Buffer/Line Driver with TRI-STATE ®
Outputs
General Description
The ’ABT244 is an octal buffer and line driver with
TRI-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented transmitter/
receiver.
n Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Nondestructive hot insertion capability
n Disable time less than enable time to avoid bus
contention
n Standard Microcircuit Drawing (SMD) 5962-9214701
Features
n Non-inverting buffers
n Output sink capability of 48 mA, source capability of
24 mA
n Output switching specified for both 50 pF and 250 pF
loads
Ordering Code
Military
Package
Package Description
Number
54ABT244J-QML
J20A
20-Lead Ceramic Dual-In-Line
54ABT244W-QML
W20A
20-Lead Cerpack
54ABT244E-QML
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Assignment for
DIP and Flatpak
Pin Assignment for LCC
DS100203-2
DS100203-1
Truth Table
OE 1
Pin
Names
Description
I 0–3
O 0–3
OE 2
I 4–7
O 4–7
OE 1 ,OE 2
Output Enable Input
(Active Low)
HXZ
HXZ
L
HHL
HH
I 0 –I 7
Inputs
L
L
L
L
L
L
O 0 –O 7
Outputs
= HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
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© 1998 National Semiconductor Corporation
DS100203
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Current Applied to Output
in LOW State (Max)
twice the rated I OL (mA)
DC Latchup Source Current
−500 mA
Over Voltage Latchup (I/O)
10V
−65˚C to +150˚C
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Ambient Temperature under Bias
−55˚C to +125˚C
Junction Temperature under Bias
Ceramic
−55˚C to +175˚C
V CC Pin Potential to Ground Pin
−0.5V to +7.0V
−55˚C to +125˚C
Input Voltage (Note 2)
−0.5V to +7.0V
Supply Voltage
Military
Input Current (Note 2)
−30 mA to +5.0 mA
+4.5V to +5.5V
Voltage Applied to Any Output
in the Disabled or
Power-Off State
Minimum Input Edge Rate
(
D
V/
D
t)
Data Input
50 mV/ns
−0.5V to 5.5V
Enable Input
20 mV/ns
in the HIGH State
−0.5V to V CC
DC Electrical Characteristics
Symbol
Parameter
ABT244
Units
V CC
Conditions
Min Typ Max
V IH Input HIGH Voltage 2.0 V Recognized HIGH Signal
V IL Input LOW Voltage 0.8 V Recognized LOW Signal
V CD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA
V OH Output HIGH Voltage 54ABT 2.5 V Min I OH = −3 mA
54ABT 2.0 V Min I OH = −24 mA
V OL Output LOW Voltage 54ABT 0.55 V Min I OL = 48 mA
I IH Input HIGH Current 5 µA Max V IN = 2.7V (Note 4)
5 V IN = V CC
I BVI Input HIGH Current Breakdown Test 7 µA Max V IN = 7.0V
I IL Input LOW Current −5 µA Max V IN = 0.5V (Note 4)
−5 V IN = 0.0V
V ID Input Leakage Test 4.75 V 0.0 I ID = 1.9 µA
All Other Pins Gro unded
I OZH Output Leakage Current 50 µA 0 − 5.5V V OUT = 2.7V; OE n = 2.0V
I OZL Output Leakage Current −50 µA 0 − 5.5V V OUT = 0.5V; OE n = 2.0V
I OS Output Short-Circuit Current −100 −275 mA Max V OUT = 0.0V
I CEX Output High Leakage Current 50 µA Max V OUT = V CC
I ZZ Bus Drainage Test 100 µA 0.0 V OUT = 5.5V; All Others GND
I CCH Power Supply Current 50 µA Max All Outputs HIGH
I CCL Power Supply Current 30 mA Max All Outputs LOW
I CCZ Power Supply Current 50 µA Max OE n = V CC ;
All Others at V CC or Ground
I CCT Additional I CC /Input Outputs Enabled 2.5 mA Max V I = V CC − 2.1V
Outputs TRI-STATE 2.5 mA Enable Input V I = V CC − 2.1V
Outputs TRI-STATE 50 µA Data Input V I = V CC − 2.1V
All Others at V CC or Ground
I CCD Dynamic I CC No Load mA/ Max Ou tputs Open
(Note 4) 0.1 MHz OE n = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions
is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Note 3: For 8 bits toggling, I CCD < 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
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AC Electrical Characteristics
Symbol
Parameter
54ABT
Units
Fig.
No.
T A = −55˚C to +125˚C
V CC = 4.5V–5.5V
C L = 50 pF
Min
Max
t PLH
Propagation Delay
1.0
5.3
ns
Figure 5
t PHL
Data to Outputs
1.0
5.0
t PZH
Output Enable
0.8
6.5
ns
Figure 4
t PZL
Time
1.2
7.9
t PHZ
Output Disable
1.2
7.6
ns
Figure 4
t PLZ
Time
1.0
7.9
Capacitance
Symbol
Parameter
Typ
Units
Conditions
T A = 25˚C
C IN
Input Capacitance
5.0
pF
V CC = 0V
C OUT (Note 5)
Output Capacitance
9.0
pF
V CC = 5.0V
Note 5: C OUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
t PLH vs Temperature (T A )
C L = 50 pF, 1 Output Switching
t PHL vs Temperature (T A )
C L = 50 pF, 1 Output Switching
DS100203-11
DS100203-12
Dashed lines represent design characteristics; for specified guarantees refer to AC Characteristics Table.
3
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Capacitance (Continued)
t PLH vs Load Capacitance
1 Output Switching, T A = 25˚C
t PHL vs Load Capacitance
1 Output Switching, T A = 25˚C
DS100203-13
DS100203-14
t PLH vs Load Capacitance
8 Outputs Switching, T A = 25˚C
t PHL vs Load Capacitance
8 Outputs Switching, T A = 25˚C
DS100203-15
DS100203-16
t PZL vs Temperature (T A )
C L = 50 pF, 1 Output Switching
t PLZ vs Temperature (T A )
C L = 50 pF, 1 Output Switching
DS100203-17
DS100203-18
Dashed lines represent design characteristics; for specified guarantees refer to AC Characteristics Table.
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Capacitance (Continued)
t PZH vs Temperature (T A )
C L = 50 pF, 1 Output Switching
t PHZ vs Temperature (T A )
C L = 50 pF, 1 Output Switching
DS100203-19
DS100203-20
t PZH vs Temperature (T A )
C L = 50 pF, 8 Outputs Switching
t PHZ vs Temperature (T A )
C L = 50 pF, 8 Outputs Switching
DS100203-21
DS100203-22
t PZL vs Temperature (T A )
C L = 50 pF, 8 Outputs Switching
t PLZ vs Temperature (T A )
C L = 50 pF, 8 Outputs Switching
DS100203-23
DS100203-24
Dashed lines represent design characteristics; for specified guarantees refer to AC Characteristics Table.
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