100331.pdf

(150 KB) Pobierz
August 1998
100331
Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP C ), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP n ), Direct
Set (SD n ) and Direct Clear (CD n ) inputs. Data enters a mas-
ter when both CP n and CP C are LOW and transfers to a
slave when CP n or CP C (or both) go HIGH. The Master Set,
Master Reset and individual CD n and SD n inputs override
the Clock inputs. All inputs have 50 k
Features
n 35% power reduction of the 100131
n 2000V ESD protection
n Pin/function compatible with 100131
n Voltage compensated operating range = −4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)
5962-9153601
W
pull-down resistors.
Logic Symbol
Pin Names
Description
CP 0 –CP 2
Individual Clock Inputs
CP C
Common Clock Input
D 0 –D 2
Data Inputs
CD 0 –CD 2
Individual Direct Clear Inputs
SD n
Individual Direct Set Inputs
MR
Master Reset Input
MS
Master Set Input
Q 0 - Q 2
Data Outputs
Q 0 –Q 2
Complementary Data Outputs
DS100300-1
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100300-3
DS100300-2
© 1998 National Semiconductor Corporation
DS100300
www.national.com
776588709.058.png 776588709.069.png 776588709.079.png 776588709.090.png 776588709.001.png 776588709.010.png 776588709.011.png 776588709.012.png 776588709.013.png 776588709.014.png 776588709.015.png 776588709.016.png 776588709.017.png
Logic Diagram
DS100300-5
Truth Tables
Asynchronous Operation
(Each Flip-Flop)
Synchronous Operation
(Each Flip-Flop)
Inputs
Outputs
D n
CP n
CP C
MS
MR
Q n (t+1)
SD n
CD n
Inputs
Outputs
X
X
X
H
L
H
D n
CP n
CP C
MS
MR
Q n (t+1)
X
X
X
L
H
L
SD n
CD n
X
X
X
H
H
U
L
N
L
L
L
L
H N L
L
L
H
L
L N L
L
L
H
L N L
L
H
X
L
L
L
L
Qn(t)
X
H
X
L
L
Qn(t)
X
X
H
L
L
Qn(t)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
U = Undefined
t = Time before CP Positive Transition
t+1 = Time after CP Positive Transition
N
= LOW to HIGH Transition
www.national.com
2
776588709.018.png 776588709.019.png 776588709.020.png 776588709.021.png 776588709.022.png 776588709.023.png 776588709.024.png 776588709.025.png 776588709.026.png 776588709.027.png 776588709.028.png 776588709.029.png 776588709.030.png 776588709.031.png 776588709.032.png 776588709.033.png 776588709.034.png 776588709.035.png 776588709.036.png 776588709.037.png 776588709.038.png 776588709.039.png 776588709.040.png 776588709.041.png 776588709.042.png 776588709.043.png 776588709.044.png
 
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T STG )
Input Voltage (DC)
V EE to +0.5V
Output Current
(DC Output HIGH)
−50 mA
ESD (Note 2)
£
2000V
Recommended Operating
Conditions
Case Temperature (T C )
Military −55˚C to +125˚C
Supply Voltage (V EE ) −5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
−65˚C to +150˚C
Maximum Junction Temperature (T J )
Ceramic
+175˚C
Pin Potential to
Ground Pin (V EE )
−7.0V to +0.5V
Military Version
DC Electrical Characteristics
V EE = −4.2V to −5.7V, V CC = V CCA = GND, T C = −55˚C to +125˚C
Symbol
Parameter
Min
Max
Units
T C
Conditions
Notes
V IN = V IH
(Max)
or V IL (Min)
V OH
Output HIGH Voltage
−1025
−870
mV
0˚C to
Loading with
50
(Notes 3,
4, 5)
W
to −2.0V
+125˚C
−1085
−870
mV
−55˚C
V OL
Output LOW Voltage
−1830
−1620
mV
0˚C to
+125˚C
−1830
−1555
mV
−55˚C
V IN = V IH
(Min)
or V IL (Max)
V OHC
Output HIGH Voltage
−1035
mV
0˚C to
Loading with
50 W to −2.0V
(Notes 3,
4, 5)
+125˚C
−1085
mV
−55˚C
V OLC
Output LOW Voltage
−1610
mV
0˚C to
+125˚C
−1555
mV
−55˚C
V IH
Input HIGH Voltage
−1165
−870
mV
−55˚C to
Guaranteed HIGH Signal
(Notes 3,
4, 5, 6)
+125˚C
for all Inputs
V IL
Input LOW Voltage
−1830
−1475
mV
−55˚C to
Guaranteed LOW Signal
(Notes 3,
4, 5, 6)
+125˚C
for all Inputs
I IL
Input LOW Current
0.50
µA
−55˚C to
V EE = −4.2V
(Notes 3,
4, 5)
+125˚C
V IN = V IL (Min)
I IH
Input HIGH Current
240
µA
0˚C to
V EE = −5.7V
V IN = V IH (Max)
(Notes 3,
4, 5)
+125˚C
340
µA
−55˚C
I EE
Power Supply Current
−130
−50
mA
−55˚C to
Inputs Open
(Notes 3,
4, 5)
+125˚C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing V OH /V OL .
3
www.national.com
776588709.045.png 776588709.046.png 776588709.047.png 776588709.048.png 776588709.049.png 776588709.050.png 776588709.051.png 776588709.052.png 776588709.053.png 776588709.054.png 776588709.055.png 776588709.056.png 776588709.057.png 776588709.059.png 776588709.060.png 776588709.061.png 776588709.062.png 776588709.063.png 776588709.064.png 776588709.065.png 776588709.066.png 776588709.067.png 776588709.068.png 776588709.070.png 776588709.071.png 776588709.072.png 776588709.073.png 776588709.074.png
 
AC Electrical Characteristics
V EE = −4.2V to −5.7V, V CC = V CCA = GND
Symbol
T C = −55˚C
T C = +25˚C
T C = +125˚C
Parameter
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
f max
Toggle Frequency
400
400
400
MHz
Figures 2, 3
(Note
10)
t PLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
ns
t PHL
CP C to Output
Figures 1, 3
t PLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
ns
t PHL
CP n to Output
t PLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
CP n ,CP C =L
Figures
1, 4
(Notes
7, 8,
9)
t PHL
CD n ,SD n to Output
ns
t PLH
0.50
2.40
0.60
2.10
0.50
2.50
CP n ,CP C =H
t PHL
t PLH
Propagation Delay
0.70
2.70
0.80
2.60
0.80
2.90
CP n ,CP C =L
t PHL
MS, MR to Output
ns
t PLH
0.70
2.90
0.80
2.80
0.80
3.10
CP n ,CP C =H
t PHL
t TLH
Transition Time
0.20
1.40
0.20
1.40
0.20
1.40
ns
Figures 1, 3, 4
t THL
20% to 80%,80%to 20%
t s
Setup Time
Figure 5
D n
1.00
0.80
0.90
(Note
10)
CD n ,SD n (Release Time)
1.50
1.30
1.60
ns
Figure 4
MS, MR (Release Time)
2.50
2.30
2.50
t h
Hold Time D n
1.50
1.30
1.60
ns
Figure 5
t pw (H)
Pulse Width HIGH
CP n ,CP C ,CD n ,
2.00
2.00
2.00
ns
Figures 3, 4
SD n , MR, MS
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C. Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).
www.national.com
4
776588709.075.png 776588709.076.png 776588709.077.png 776588709.078.png 776588709.080.png 776588709.081.png 776588709.082.png 776588709.083.png 776588709.084.png 776588709.085.png 776588709.086.png 776588709.087.png 776588709.088.png 776588709.089.png 776588709.091.png 776588709.092.png 776588709.093.png 776588709.094.png 776588709.095.png 776588709.096.png 776588709.097.png 776588709.098.png 776588709.099.png 776588709.100.png 776588709.002.png 776588709.003.png 776588709.004.png 776588709.005.png
 
Test Circuits
DS100300-6
FIGURE 1. AC Test Circuit
DS100300-7
Notes:
V CC ,V CCA = +2V, V EE = −2.5V
L1 and L2 = Equal length 50
W
impedance lines
R T = 50
terminator internal to scope
Decoupling 0.1 µF from GND to V CC and V EE
All unused outputs are loaded with 50
W
W
to GND
C L = Fixture and stray capacitance
£
3pF
FIGURE 2. Toggle Frequency Test Circuit
5
www.national.com
776588709.006.png 776588709.007.png 776588709.008.png 776588709.009.png
 

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin