M27C1001.pdf

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M27C1001
1 Mbit (128Kb x8) UV EPROM and OTP EPROM
5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
FAST ACCESS TIME: 35ns
LOW POWER CONSUMPTION:
– Active Current 30mA at 5Mhz
– Standby Current 100 m A
PROGRAMMING VOLTAGE: 12.75V
32
32
1
PDIP32 (B)
1
0.25V
PROGRAMMING TIME: 100 m s/byte (typical)
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 05h
±
FDIP32W
(F)
DESCRIPTION
The M27C1001 is a 1 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and is
organized as 131,072 words of 8 bits.
The FDIP32W (window ceramic frit-seal package)
and the LCCC32W (leadless chip carrier package)
have a transparent lids which allow the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C1001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
LCCC32W (L)
PLCC32 (C)
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
V CC
V PP
17
8
A0-A16
Q0-Q7
Table 1. Signal Names
A0-A16
Address Inputs
P
M27C1001
Q0-Q7
Data Outputs
E
E
Chip Enable
G
G
Output Enable
P
Program
V PP
Program Supply
V SS
V CC
Supply Voltage
AI00710B
V SS
Ground
September 1998
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M27C1001
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
V PP
1
2
3
4
5
6
7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V CC
A16
P
A15
NC
1
32
A12
A14
A7
A14
A7
A13
A6
A5
A13
A6
A5
A8
A9
A8
A4
A3
A2
A9
A4
A3
A2
8
A11
G
M27C1001
9
M27C1001
25
A11
9
10
11
12
13
14
15
16
G
A10
A1
A0
Q0
A10
A1
A0
Q0
E
E
Q7
Q7
Q6
17
Q1
Q2
Q5
Q4
V SS
Q3
AI00712
AI00711
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
DEVICE OPERATION
The operating modes of the M27C1001 are listed
in the Operating Modes table. A single power sup-
ply is required in the read mode. All inputs are TTL
levels except for V PP and 12V on A9 for Electronic
Signature.
Read Mode
The M27C1001 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(t AVQV ) is equalto the delay from E to output (t ELQV ).
Data is availableat the output after a delay of t GLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
at least t AVQV -t GLQV .
Standby Mode
The M27C1001 has a standby mode which re-
duces the supply current from 30mA to 100 m A. The
M27C1001 is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
A11
1
32
G
A9
A10
A8
E
A13
Q7
A14
Q6
NC
P
Q5
Q4
V CC
8
M27C1001
(Normal)
25
Q3
V PP
9
24
V SS
A16
Q2
A15
Q1
A12
Q0
A7
A0
A6
A5
A1
A2
A4
16
17
A3
AI01151B
Warning: NC = Not Connected.
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M27C1001
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (3)
T A
–40 to 125
°
C
T BIAS
Temperature Under Bias
–50 to 125
°
C
T STG
Storage Temperature
–65 to 150
°
C
V IO (2)
Input or Output Voltages (except A9)
–2 to 7
V
V CC
Supply Voltage
–2 to 7
V
V A9 (2)
A9 Voltage
–2 to 13.5
V
V PP Program Supply Voltage –2 to 14 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V CC +0.5V with possible overshoot to V CC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
E
G
P
A9
V PP
Q0 - Q7
Read
V IL
V IL
X
X
V CC or V SS
Data Out
Output Disable
V IL
V IH
X
X
V CC or V SS
Hi-Z
Program
V IL
V IH
V IL Pulse
X
V PP
Data In
Verify
V IL
V IL
V IH
X
V PP
Data Out
Program Inhibit
V IH
X
X
X
V PP
Hi-Z
Standby
V IH
X
X
X
V CC or V SS
Hi-Z
Electronic Signature
V IL
V IL
V IH
V ID
V CC
Codes
Note :X =V IH or V IL ,V ID = 12V
±
0.5V
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
V IL
0
0
1
0
0
0
0
0
20h
Device Code
V IH
0
0
0
0
0
1
0
1
05h
Two Line Output Control
BecauseEPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows :
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of thesetwo control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
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M27C1001
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
3
10ns
3
20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
Input and Output Timing Ref. Voltages
1.5V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
0V
3.3k W
DEVICE
UNDER
TEST
OUT
Standard
C L
2.4V
2.0V
0.8V
0.4V
C L = 30pF for High Speed
C L = 100pF for Standard
C L includes JIG capacitance
AI01822
AI01823B
Table 6. Capacitance (1)
(T A =25 ° C, f = 1 MHz )
Symbol
Parameter
Test Condition
Min
Max
Unit
C IN
Input Capacitance
V IN =0V
6
pF
C OUT
Output Capacitance
V OUT =0V
12
pF
Note: 1. Sampled only, not 100% tested.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I CC , has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitiveand inductiveloading of the deviceat the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1
F ceramic
capacitor be used on every device between V CC
and V SS . This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7
m
F bulk electrolytic capacitor should be used
between V CC and V SS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
m
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M27C1001
Table 7. Read Mode DC Characteristics (1)
(T A = 0 to 70
°
C, –40 to 85
°
C or –40 to 125
°
C; V CC =5V
±
5% or 5V
±
10%; V PP =V CC )
Symbol
Parameter
Test Condition
Min
Max
Unit
I LI
Input Leakage Current
0V
3
V IN 3
V CC
±
10
m
A
I LO
Output Leakage Current
0V
3
V OUT
3
V CC
±
10
m
A
E=V IL ,G=V IL ,
I OUT = 0mA, f = 5MHz
I CC
Supply Current
30
mA
I CC1
Supply Current (Standby) TTL
E = V IH
1
mA
I CC2
Supply Current (Standby) CMOS
E > V CC – 0.2V
100
m
A
I PP
Program Current
V PP =V CC
10
m
A
V IL
Input Low Voltage
–0.3
0.8
V
(2)
V IH
Input High Voltage
2
V CC +1
V
V OL
Output Low Voltage
I OL = 2.1mA
0.4
V
Output High Voltage TTL
I OH = –400
m
A
2.4
V
V OH
Output High Voltage CMOS
I OH = –100 m A
V CC – 0.7
V
Note:
1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .
2. Maximum DC voltage on Output is V CC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(T A = 0 to 70
°
C, –40 to 85
°
C or –40 to 125
°
C; V CC =5V
±
5% or 5V
±
10%; V PP =V CC )
M27C1001
Symbol
Alt
Parameter
Test Condition
Unit
-45 (3)
-60
-70
Min
Max
Min
Max
Min
Max
Address Valid to
Output Valid
t AVQV
t ACC
E=V IL ,G=V IL
45
60
70
ns
Chip Enable Low to
Output Valid
t ELQV
t CE
G=V IL
45
60
70
ns
Output Enable Low
to Output Valid
t GLQV
t OE
E=V IL
25
30
35
ns
Chip Enable High to
Output Hi-Z
(2)
t EHQZ
t DF
G=V IL
0
25
0
30
0
30
ns
Output Enable High
to Output Hi-Z
(2)
t GHQZ
t DF
E=V IL
0
25
0
30
0
30
ns
Address Transition to
Output Transition
t AXQX
t OH
E=V IL ,G=V IL
0
0
0
ns
Notes: 1. V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurament conditions.
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