00329965 - Quasi-Parallel Resonant Dc Link Inverter With Improved Pwm Capability.pdf - INWERTERY - j_czaja1

sively [14. Their advantages over hard switching inverters are

low switching loss, low EM1 and acoustic noise, high power den-

sity and high dynamic performance resulting from high switching

frequency. They also have disadvantages. An early resonant

inverter suggested by Divan [I] has high voltage and current

stresses and subharmonic problems due to discrete pulse modula-

tion (DPM). Other types of soft switching PWM inverter have

been suggested, which use a parallel resonant DC-link (PRDCL)

which provides variable DC-link pulse width [2, 31. They usually

have a few additional switches. Although the quasi-resonant DC-

link (QRDCL) inverter suggested by Malesani [4] has only two

additional switches, it still has restricted PWM capability. In this

Letter, a new quasi-parallel resonant soft switching PWM inverter

is proposed to overcome the aforementioned drawbacks of reso-

nant link inverters. That is, the proposed quasi-parallel resonant

DC-link (QPRDCL) inverter has minimum voltage stress and

improved PWM capability by adding two switches.

Table 1

Table 1: Circuit performance

Power bandwidth (V,=IOV P-P)

Bandwidth ( Vm=2V P-P, RL=IOkR, CL=20pF)

Phase shift at bandwidth

OfTset voltage

Voltage gain (V,.=ZV

218MHz

220MHz

-127

1.75mV

1 (R,=lOkR)

1 (RL=lkR)

O.pryR,=soO~)

+ 1290Vius -I 33OVius

+56.4ns 47.8ns

41dB

P-P)

Slew-rate (R,=lOkW. CL=20pF)

Settling time (-5 to 5V pulse to 0.1%)

Input voltage range

THD (V,,=2V P-P, RL=500W,f=100kHz)

Total sunnlv current

+10.8V -12v

18mA

Conclusions: A new design approach for high accuracy and high

speed voltage followers has been presented. The conventional

tradeoff between speed and accuracy has been overcome by apply-

ing feedfonvard to make the main amplifier float. Theoretically,

the new buffer has virtually no slew-rate limitations. Simulations

show that more than 1300V/ps slew rate and less than 6011s set-

tling time can he obtained relatively easily. The handwidth in this

new design is increased from -35MHz in the conventional feed-

hack buffer to -220MHz with a phase margin of 53”. With the

improvement in speed, the gain accuracy is also improved. This

improvement in accuracy comes from the enhanced gain and the

increased speed in the core floating amplifier.

In the new buffer design presented here the improved perform-

ance has been obtained with some additional circuity, which does

cause a reduction in the input and output voltage headroom. Also

the power-supply current is higher in the new design. However,

these ‘cost penalties’ are relatively minor compared with the suh-

stantial benefits that the circuit exhihits. For a given semiconduc-

tor technology, the new design yields far higher performance than

can he achieved using a conventional buffer design. The main

application of this new approach is in the design of monolithic

integrated circuit voltage followers.

D,l

Fig. 1 Circuit configuration of

proposed QPRDCL inverter

Dll1

D1 z

Crl +

Acknowledgment: The authors would like to thank Analog Devices

(Precision Monolithic), Santa Clara, USA for supporting this

research.

0 IEE 1994

Electronics Letters Online No: I9941270

W. J. Su and F. J. Lidgey (School of Engineering, Oxford Brookes

University, Headingron, Oxford OX3 OBP, United Kingdom)

5 September 1994

Fig. 2 Equivalent circuit of

proposed QPRDCL inverter

References

Principle of operation: The circuit configuration of the proposed

QPRDCL inverter is shown in Fig. 1. The QPRDCL consists of

two switching devices Sa, and Sa,, two diodes D, and D,, resonant

inductor L, and resonant capacitors C,, and C,,. In this case, C,,

is the main resonant capacitor and the auxiliary capacitor C,, is

used to reverse the resonant inductor current i,. Because the reso-

nant inductor L, is sufficiently smaller than the load inductance,

the inverter with three phase load can he replaced by current

source I, during the switching period. Fig. 2 shows the equivalent

circuit of the proposed QPRDCL inverter for explanation of the

link operation. Operation modes consist of seven intervals and

related waveforms are shown in Fig. 3. At the early stage of the

first interval, the output load current I, flows through either

switch Sa, or antiparallel diode D,, of switch So, and the second

auxiliary switch Sa, is in the off state. If the switching status of the

inverter needs to he changed, switch S,, is turned on with zero

current condition for initialising the resonant inductor current iL, .

As iL, reaches the previously fixed initialising current I;, the reso-

nance between L, and C,, occurs by turning off Sa, with the zero

voltage condition. The main resonant capacitor voltage vcrl

decreases resonantly from the DC source voltage V, to 0 and

thereafter the resonant inductor current il, freewheels through

antiparallel diodes of inverter switches. The freewheeling duration

is controllable and thus the link pulse position can he located at

any position which is given by the PWM controller. In this mode,

all inverter switches are turned on under zero voltage. Some time

after, switch So, is turned off under the zero voltage condition and

the resonant inductor current iL, is reversed by the resonance

between L, and C,,. When this mode is completed, the inductor

WIDLAR. R.J.: ‘Design technique for monolithic operational

amplifiers’, IEEE J. Solid-State Circuits, 1969, SC-4, (4), pp. 18&

191

ERDI. G.: ‘A 300 Vip monolithic voltage follower’, IEEE J. Solid-

Slate Circuits, 1979, SC-14, (6). pp. 1059-1065

GREBENE, A.B.: ‘Bipolar and MOS analog integrated circuit design’

(John Wiley & Sons Inc., USA 1984), pp. 383-387

Quasi-parallel resonant DC link inverter with

improved PWM capability

Y.-C. Jung and G.-H. Cho

Indexing terms: Inverters, Pulse width modulation

A quasi-parallel resonant DC-link (QPRDCL) circuit with

improved PWM capability is proposed for the zero voltage

switching (ZVS) three phase PWM inverter. The circuit has

minimum voltage stresses and improved PWM capability due to

the flexible selectability of the odoff instants of the resonant link.

Introduction: Many resonant DC-link inverters with zero-voltage

or zero-current switching have been proposed and studied exten-

ELECTRONICS LE77ERS

27th October 1994

Vol. 30

No. 22

1827

current i, freewheels again through the inverter switches. When

the total zero voltage duration, I, - t,, equals a proper value which

is pre-calculated by the PWM controller, the switches of the

inverter selected according to the modulation strategy are turned

off under the zero voltage condition. A new resonance between L,

and C,, occurs and the main capacitor voltage vLrl increases up to

the DC source voltage V,. The residual current flows through

diode D,, and lastly becomes zero. In this period, switch So, can

be turned on under the zero voltage condition. One switching

cycle of the QPRDCL is completed at the end of this mode.

HE. J., and MOHAN, N.: ‘Parallel resonant dc link circuit - A novel

zero switching loss topology with minimum voltage stresses’. IEEE

Power Electron. Spec. Conf. Rec., 1989, pp. 1006-1012

3 CHO,I.G., KIM. H.S., and CHO, G.H.: ‘Novel soft switching PWM

converter using a parallel resonant dc-link’. IEEE Power Electron.

Spec. Conf. Rec., 1991, pp. 241-241

quasi resonant dc link converter for full-range PWM. IEEE-

APEC, 1992, pp. 412418

MALESANI, L., TENTI, P., TOMASIN. P., and TOIGO, V.: ‘High efficiency

Effective multipriority scheme for DQDB

MAC protocol

E.T. Weaver, R. Ahmad and F. Halsall

Indexing rerm: Metropolitan area networks

The authors propose a modification to the priority scheme

specified in the DQDB standard enabling it to operate effectively

on large high-speed networks requiring the use of the BWB

mechanism to achieve fairness. The modified priority scheme is

also capable of operating with the BWB mechanism disabled and

is therefore general in its application. Results of a simulation

analysis are presented demonstrating the effectiveness of the

modified priority scheme for a number of different scenarios.

tl tZ t3

t6 ‘7

tL t5

Fig. 3 Typical waveforms of QPRDCL circuit

Experimental results: To verify the operational principles, the pro-

totype QPRDCL inverter was designed and built to have a maxi-

mum power rating of Po,,.,, = 6kVA at 20kHz switching

frequency. The circuit parameters used in the experiment are given

as follows: L, = 20m, C,, = 45nF. C,, = 205nF.

Introduction: The standardised and recommended medium access

control (MAC) protocol for metropolitan area networks (MANS)

is the IEEE 802.6 distributed queue dual bus (DQDB) MAC pro-

tocol [I]. Although standardised, many of the protocol’s specified

services are still areas of current research. The problem of unfair

medium-access experienced by nodes on DQDB networks with a

latency greater than one slot time has received much attention [2,

31. To overcome the protocol’s unfairness problems the bandwidth

balancing (BWB) mechanism proposed in [3] was adopted and

incorporated into the standard by the IEEE 802.6 committee.

However, the BWB mechanism only provides fair access for uni-

priority traffic under heavy-load conditions. Detailed studies and

analysis on the failure of DQDBs multipriority scheme for the

queued arbitrated (QA) access mechanism can be found in 14, 51.

’ -

Priority schemes for use with DQDB networks were proposed

loa/ 5psldlv

100VldivlOAl

5psldiv

in [6]. However, the schemes in Sections 5 and 6 of [6] are not able

IOOVldiv

to provide absolute prioritised access and cannot operate if the

BWB mechanism is not enabled. The scheme in section 7 of [6] is

div

lz3z4

Fig. 4 E.rperimenta1 waveforms

a Upper trace : main resonant capacitor voltage (vCrl)

b Upper trace : auxiliary resonant capacitor voltage (vCrl)

capable of providing absolute prioritised access and may operate

with and without the BWB mechanism enabled; this scheme, how-

ever, requires significant changes to the DQDB architecture. It is

apparent that these schemes do not offer an acceptable alternative

to the orioritv scheme soecified in the DODB standard and thus

I ,

have not been adopted by the standardisation committee.

In this Letter we propose a modification to the priority scheme

specified in the IEEE 802.6 standard [I] enabling it to operate

effectively on large high-speed networks requiring the use of the

BWB mechanism to achieve fairness.

Lower trace : resonant inductor current (iL,)

Fig. 4 shows the oscillograms of resonant inductor current and

capacitor voltages verifying the predicted waveforms.

Conclusion: In this Letter, a new soft switching PWM inverter is

presented by using the QPRDCL circuit and verified by the exper-

iment. The proposed inverter has minimum voltage and current

stresses and highly improved PWM capability by adding only two

additional switches. It is thought to be a good candidate for a

high frequency operating inverter requiring quiet and smooth cur-

rent waveforms in the medium power range.

Proposed rnodificution: The failure of the multipriority scheme

proposed in the DQDB standard [I], when operating with the

BWB mechanism enabled, is due to the lower priority nodes not

having the correct information on the higher priority load cur-

rently awaiting transmission over the network.

The proposed mechanism provides the lower priority nodes with

this additional information via the use of balancing requests

(BAL-REQs). The mechanism operates as follows : high-priority

nodes, that are forced to leave an empty slot pass to satisfy the

operation of the BWB mechanism, set a BAL-REQI bit at the

appropriate priority level (I) if they have a segment at that priority

level awaiting transmission, instead of inherently allowing an un-

set REQ-I bit to pass. Upstream nodes with a lower priority will

treat the set BAL-REQ-I bit as it would an equivalent high-prior-

ity request, therefore the balancing requests effectively inform the

lower priority nodes that higher priority nodes are active and are

sharing the bandwidth using the BWB mechanism. High-priority

nodes will use any un-set REQ-I bits at the relevant priority as

0 IEE 1994

Electronics Letters Online No: 19941239

Y.X. Jung and G.-H. Cho (Department o/ Electrical Engineering.

Korea Advanced Institute of Science and Technology 373-1, Kusong-

Dong, Yusong-Gu, Taejon, 305-701, Korea)

August 1994

References

D.M.: ‘The dc link - A new concept in

static power conversion’. IEEE-IAS Conf. Records, 1986, pp. 648-

656

1828

DIV~N.

ELECTRONICS LETTERS

27th October 7994

Vol. 30

No. 22

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