TC90A32F.PDF

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TC90A32F
Preliminary
TOSHIBA CMOS Digital Interated Circuit
Silicon Monolithic
T C 9 0 A 3 2 F
Digital Video Encoder
The TC90A32F converts a digital image’s Y, Cb and Cr signals,
which conform to ITU-R601/656 standards, to analog Y and C
composite signals for NTSC and PAL systems.
Features
•
Encodes ITU-R 601/656 format Y/Cb/Cr digital video signal
(8-bit/16-bit) to analog video signal.
•
NTSC/PAL (-B, -G, -D, -K, -I) encoder
•
Copy protection (MACROVISION Rev. 6.1/7.01)*
Weight: g (typ.)
•
Closed caption, VBID encoding
•
Various types of synchronizing signal can be generated.
•
Master/Slave Modes
•
Built-in 10-bit DAC for CVBS, Y and C
•
Y set-up 0/7.5% changeable (NTSC)
•
27-MHz system clock (can be switched between internal oscillation/outside input)
•
13.5-MHz clock output
•
Internal digital sub-carrier synthesizer
•
Interlaced or non-interlaced support
•
Can be controlled by I 2 C bus.
•
64-pin QFP
•
Single 3.3-V power supply
* : This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216 and 4,819,098 and other intellectual
property rights.
The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is
intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision.
Reverse engineering or disassembly is prohibited.
000707EBA1
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.
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TC90A32F
Block Diagram
8
Y
8
Y
10
YCDI [15:8]
10
10
Y-gain &
address sync.
Y/
Cb/Cr
demux.
8
Y-LPF
DAC
Y
YCDI [7:0]
(13.5 M → 27 M)
CVBS
10
VBLNK
C-modulation
10
Cb
9
+
DAC
CVBS/fsc
Y 8
8 Cb/Cr
8
Inter-
polation
8
10
×
Cb/Cr
8
c
10
Color bar &
ramp wave
generator
Cb/Cr
LPF
Cb/Cr
gain
(13.5 M
→
27 M)
10
+
Cr
9
DAC
C/fsc
8
8
10
Inter-
polation
×
(6.75 M → 13.5 M)
(13.5 M
→
27 M )
fsc
10
V REF
fsc-
gain
BIAS1
8
fsc
8
8
BIAS2
Address
generator
9
ROM
IFV
Closed-
caption
VBID/WSS
Copy
protection
I 2 C decoder
Sync generator
IFH
3
4
5
1/2
CSYNC
VSYNC
FID
BF
SCL
SDA
/RESET
MODE
IMS [2:0]
TMS [3:0]
TESTIO [4:0]
XI
XO
CK270
CK130
HSYNC
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TC90A32F
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TMS2
49
32
V REF
TMS1
50
31
BIAS1
TMS0
51
30
AGND
DV DD
52
29
CVBS/fsc
XI
53
28
AV CC
XO
54
27
Y
DGND
55
26
AGND
CK270
56
TC90A32F
(top view)
25
C/fsc
DV DD
57
24
AV CC
CK130
58
23
DV DD
DGND
59
22
DGND
IFV
60
21
CSYNC
IFH
61
20
HSYNC
VBLNK
62
19
VSYNC
YCDI15
63
18
FID
YCDI14
64
17
BF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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TC90A32F
Pin Names
Pin No.
Name
I/O
Function
Notes
1
YCDI13
I
2
YCDI12
I
3
YCDI11
I
Pixel data input pins * 1
4
YCDI10
I
5
YCDI9
I
6
YCDI8
I
7
DV DD
Digital power supply
8
YCDI7
I
9
YCDI6
I
Pixel data input pins * 2
10
YCDI5
I
11
YCDI4
I
12
DGND
Digital GND
13
YCDI3
I
14
YCDI2
I
Pixel data input pins * 2
15
YCDI1
I
16
YCDI0
I
17
BF
O
Burst flag pulse output (synchronized with analog output)
18
FID
O
Field ID output (synchronized with analog output)
19
VSYNC
O
Vertical synchronization signal output
(synchronized with analog output)
20
HSYNC
O
Horizontal synchronization signal output
(synchronized with analog output)
21
CSYNC
O
Composite sync output (synchronized with analog output)
22
DGND
Digital GND
23
DV DD
Digital power supply
24
AV CC
Analog power supply for DAC
For DAC
Dynamic range of analog
output is set by V REF .
Output voltage:
1.5 V p-p max
(V DD to V DD − 1.5 V)
25
C/fsc
O
Analog C-signal/fsc output (for testing)
26
AGND
Analog GND for DAC
27
Y
O
Analog Y-signal output
28
AV CC
Analog power supply for DAC
29
CVBS/fsc
O
Analog CVBS/fsc output
30
AGND
Analog GND for DAC
31
BIAS1
Bias pin 1 for DAC
32
V REF
Reference voltage input for DAC
33
BIAS2
Bias pin 2 for DAC
34
IMS2
I
MSB
35
IMS1
I
Input mode setting pins
36
IMS0
I
LSB
37
DGND
Digital GND
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TC90A32F
Pin No.
Name
I/O
Function
Notes
38
TESTO4
O
MSB
39
TESTO3
O
40
TESTO2
O
Output pins for testing (Connect to digital GND.)
41
TESTO1
O
42
TESTO0
O
LSB
43
DV DD
Digital power supply
44
SDA
I/O I 2 C bus data
* 5-V withstand
45
SCL
I
I 2 C bus clock
46
/RESET
I
RESET input (L: RESET)
47
MODE
I
NTSC/PAL selection (L: NTSC/H: PAL)
48
TMS3
I
MSB
49
TMS2
I
Input pins for testing (Connect to digital GND.)
50
TMS1
I
51
TMS0
I
LSB
52
DV DD
Digital power supply
53
XI
I
X’tal connection/27-MHz clock input
54
XO
O
X’tal connection
55
DGND
Digital GND
56
CK270
O
27-MHz clock output
57
DV DD
Digital power supply
58
CK130
O
13.5-MHz clock output
59
DGND
Digital GND
60
IFV
I/O Vertical synchronous signal for I/F input/output
61
IFH
I/O Horizontal synchronous signal for I/F input/output
62
VBLNK
I/O Video blanking signal for I/F input/output
63
YCDI15
I
Pixel data input pins * 1
64
YCDI14
I
Note1: Pixel data input pins * 1 (YCDI [15:8])
ITU-R601 8-Bit Master/Slave Modes, ITU-R656 Mode: Fixed L-input
ITU-R601 16-Bit Master/Slave Modes: 8-bit parallel input pins for Cb/Cr signals
Pixel data input pins * 2 (YCDI [7:0])
ITU-R601 8-Bit Master/Slave Modes, ITU-R656 Mode: Y/Cb/Cr 8-bit serial input pins
ITU-R601 16-Bit Master/Slave Modes: 8-bit parallel input pins for Y-signal
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