52704di.pdf

design

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Edited by Bill Travis

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Circuit provides 4- to 20-mA loop

for microcontrollers

Robert Most, Dow Corning Corp, Auburn, MI

T HE 4- TO 20-MA current loop is ubiq-

15V

uitous in the world of controls in

manufacturing plants. Discrete log-

ic, microprocessors, and micro-

controllers easily cover the digital

portions of control schemes, such as lim-

it switches, pushbuttons, and signal

lights. Interfacing a 4- to 20-mA output

to a rudimentary microcontroller can be

problematic. A built-in A/D converter

would be nice, but such a device is some-

times unavailable in the “economy” line

of these processors. Serial 4- to 20-mA

chips exist but are relatively expensive

and require serial programming and in-

volve microcontroller overhead. Most

lower end chips lack dedicated serial

ports and require pin-programming.

This circuit is a low-cost alternative

that provides not only a 4- to 20-mA out-

put, but also a digital feedback signal that

indicates an open wire in the current loop

( Figure 1 ). One output-port pin sets the

current, and one input-port pin monitors

an open circuit in the loop wire. The cir-

cuit does not require the open-loop feed-

back portion of the circuit for the current

loop to operate; you can omit it for fur-

ther cost savings.

The circuit derives its drive from a sim-

ple timer output in the microcontroller.

The duty cycle of the timer determines

the output current of the circuit. The in-

put RC network in front of the first op-

erational-amplifier signal conditions the

pulse train from the processor, so that the

op amp interprets it as a dc voltage. In ad-

dition, the network ensures that the min-

imum input voltage is close to 100 mV,

even if the input is at ground potential.

This minimum voltage ensures that the

feedback loop of the first op amp does

not fold back to the positive rail when

you cut off npn transistor Q 1 . If you use

a dual supply, the transistor has the ad-

15V

100

Figure 1

100

1/2

TL032

680

Q 3

2N3906

8.2k

27k

FROM

PROCESSOR

TIMER

+ 1/2

TL032

100k

Q 2

I OUT

4.7

Q 1

2N3906

2N3904

56k

R L

PROCESSOR

INPUT PORT

140

27k

This configuration provides both a 4- to 20-mA loop and an open-circuit indication.

ditional voltage swing below ground po-

tential to keep it in its active region and

does not cut off. The emitter resistor of

npn transistor Q 1 sets the current span of

the circuit. With a 5V drive from the mi-

crocontroller, the output current is 20

mA. A grounded input results in less than

1 mA. A duty cycle of 12.5% drives the

loop at 4 mA and exhibits linear control

to full scale. Although it may not be

mandatory, most current loops prefer a

grounded return path. The purpose of

the second operational amplifier is to

provide a current source, rather than the

current sink of the first stage, and the

grounded return path. Hence, pnp tran-

sistor Q 3 provides this high-side drive.

Bipolar-junction transistors Q 1 and Q 3

meet cost considerations, but you could

also use MOSFETs for slightly better per-

formance.

The open-loop feedback portion of

this circuit lets the microcontroller

know that a fault condition exists on the

line. The processor can then execute

alarm, shutdown, or other control func-

tions to mitigate possible safety con-

cerns. When an open-loop condition oc-

curs, Q 3

resistor to the op

amp. The voltage developed across the

680

resistor turns on Q 2 , resulting in

a logic-one feedback to the microcon-

troller. Note that the open loop requires

at least 1 mA of current for the open in-

dication to function, which is below the

normal 4 mA—a “zero” output condi-

Circuit provides 4- to 20-mA loop

for microcontrollers........................................ 89

Minimize the short-circuit current pulse

in a hot-swap controller .............................. 90

Reduce EMI by sweeping

a power supply’s frequency ........................ 92

Get just enough boost voltage .................. 94

Processor’s PWM output controls

LCD/LED driver .............................................. 96

Method provides automatic

machine shutdown ........................................ 98

Circuit makes simple high-voltage

inverter .......................................................... 100

Publish your Design Idea in EDN . See the

What’s Up section at www.edn.com.

shunts the entire loop current

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MAY 27, 2004 | EDN 89

back through its emitter-base junction

and through the 680

design

ideas

tion for this type of control system.

Response time for a step change is ap-

proximately 500 msec, which is accept-

able for most current-loop control de-

vices, such as control valves. If the

microcontroller you select has a built-

in A/D converter, response time can de-

crease by a couple of orders of magni-

tude with the elimination of the in-

put-filtering network. Op-amp selec-

tion is important if you use a single-

supply topology. An operational ampli-

fier that can maintain stability close to

its negative, or ground, rail is an im-

portant asset.

Minimize the short-circuit current pulse

in a hot-swap controller

Jim Sherwin and Thong Huynh, Maxim Integrated Products, Sunnyvale, CA

breaker delay and limited

MOS-gate pulldown current,

many hot-swap controllers do not

limit current during the first 10 to

R S

0.006

M 1

FDS7788

tor chip. The circuit of Figure 5

can limit short-circuit current to

approximately 100A for less than

200 nsec. The pnp transistor, Q 1A ,

which triggers when the voltage

across R S reaches approximately

600 mV, drives the npn transistor,

Q 1B ,to quickly discharge M 1 ’s gate

capacitance. The steep voltage

waveform aids quick triggering of

the pnp transistor.

The oscilloscope’s ground lead

introduces an artifact, which ap-

pears as the leading-edge oscilla-

tion in Figure 6 . Again, as in Fig-

ure 4 , the apparent reverse-

overshoot current and the steep rise in the

waveform of Figure 6 arise from parasitic

series inductance in the sense-resistor

chip. C 2 connects between the gate and

source of M 1 to reduce the positive-tran-

sient step voltage applied to the gate dur-

ing a short circuit. Zener diode D 1 reduces

I D(ON) by limiting V GS to less than the 7V

available from the MAX4272. Although D 1

12V IN

12V OUT

sec following a shorted out-

put. The result can be a brief flow

of several hundred amperes. A

simple external circuit can count-

er this problem by minimizing the

initial current spike and terminat-

ing the short circuit

within 200 to 500 nsec. A

typical 12V, 6A, hot-swap-con-

troller circuit contains, as do many

others, slow and fast comparators

with trip thresholds of 50 and 200 mV

( Figure 1 ). The 6-m

SENSE

GATE

MAX4272ESA

STAT

POR

CSPD

GND

CTIM

Figure 1

C 1

22 nF

A typical hot-swap controller circuit exhibits a 30- sec short-

circuit current pulse of 400A peak.

sense resistor, R S ,

allows a nominal slow-comparator trip at

8.3A for overload conditions and a fast-

comparator trip at 33.3A for short cir-

cuits. Only circuit resistances limit the

initial short-circuit current spike during

a period that includes the fast-compara-

tor delay and the 30

resistances. The waveform recorded dur-

ing a short circuit indicates a peak cur-

rent of 400 from the 2.4V peak across R S ,

decreasing to 100A in 28

sec ( Figure 2 ).

You can limit the short-circuit current

duration to less than 0.5

sec by adding

a Darlington pnp transistor, Q 1 , to speed

the gate discharge ( Figure 3 ). D 1 allows

the gate to charge normally at turn-on,

but, at turn-off, the con-

troller’s 3-mA gate-dis-

charge current is direct-

ed to the base of Q 1 .Q 1

then acts quickly to dis-

charge the gate, in less

than 100 nsec. Thus, the

high-current portion of

the short circuit is limit-

ed to slightly more than

the fast comparator’s de-

lay time of 350 nsec. The

apparent reverse over-

shoot current and the

steep rise in the wave-

form of Figure

4 arise from

parasitic series induc-

tance in the sense-resis-

sec it takes to com-

plete interruption of the short circuit by

discharging M 1 ’s gate capacitance. Vari-

ous elements, such as R S and the on-re-

sistance of M 1 , contribute to the circuit

R S

0.006

M 1

FDS7788

12V IN

12V OUT

MMBTA64FSTR-ND

FLAG-COMPARATOR

TRIGGER POINT

Q 1

D 1

MMBD4148

SENSE

GATE

VOLTAGE MEASURED ACROSS R S =6 m.

MAX4272ESA

STAT

POR

CSPD

GND

CTIM

M5 SEC CH1 –200 mV

C 1

22 nF

The short-circuit current

in Figure 1 is 400A, decreasing to 100A in

28 sec.

Figure 3

The addition of Q 1 increases the gate-pulldown current, lim-

iting the short-circuit-current duration to less than 0.5

sec.

90 EDN | MAY 27, 2004

www.edn.com

B ECAUSE OF INTERNAL circuit-

Figure 2

design

ideas

STEEP RISE AND

REVERSE OVERSHOO T

IN SENSE-RESISTOR

VOLTAGE MEASUREMENT

IS AN ARTIFACT OF

SENSE-RESISTOR PARA-

SITIC INDUCTANCE.

R S

0.006

M 1

FDS7788

12V IN

C 2

100 nF

12V OUT

R 1

100

D 1

5.1V

R 3

Q 1B

Q 1A

R 2

100

FFB2227A

M 250 nSEC CH1 –360 mV

Figure 5

SENSE GATE

Figure 4

MAX4272ESA

STAT

POR

The steep rise and reverse

overshoot in Figure 3’s circuit are artifacts of

sense-resistor parasitic inductance.

This hot-swap

controller has

fast limiting of

short-circuit-

current peaks.

CSPD

GND

CTIM

C 1

22 nF

is rated at 5.1V when biased at 5 mA, it

limits V GS to approximately 3.4V in this

circuit because only 100

A of gate-charg-

ing current (zener-bias current) is avail-

able from the IC. The limited V GS lowers

I D(ON) —at some expense to on-resist-

ance—and allows a quicker turn-off of

M 1 . You could also use D 1 and C 2 to some

advantage in figures 1 and 3 ,to reduce

I D(ON) during short circuits.

Either of the two circuits can protect a

backplane power source by minimizing

the energy dissipated when a hot-swap-

controller circuit incurs a short circuit. The

simpler circuit ( Figure 3 ) dramatically

shortens the short-circuit-current interval

to somewhat less than 500 nsec, and the

slightly more complex circuit ( Figure 5 )

reduces the peak short-circuit current to

100A, as well as truncating the pulse width

to less than 200 nsec. You can apply either

technique to most hot-swap-controller

circuits. Individual results vary according

to the impedance of the power source, the

impedance of the short circuit, and the

quality and attack time of the short circuit

itself. Note that it is inordinately difficult

to achieve a repeatable low-resistance short

circuit by manual manipulation of a

shorting bar. You require careful lay-

out and low-ESR capacitors to create a

power source with very low ESR.

M 100 nSEC CH1 –520 mV

Figure 6

This waveform depicts the

short-circuit-current peaks for the circuit in

Figure 4.

Reduce EMI by sweeping a power supply’s frequency

John Betten, Texas Instruments, Dallas, TX

notorious noise generators. You

should prevent this noise, which is

conducted, radiated, or both, from re-

turning to the input source, where it can

potentially wreak havoc on other devices

operating from the same input power.

The goal of an EMI (electromagnetic-in-

terference) filter is to block this noise and

provide a low-impedance path back to

the noise source. The larger the noise, the

greater the size, expense, and difficulty of

the filter design. Power supplies that op-

erate at a fixed frequency have their

largest EMI emission at this fundamen-

tal, fixed frequency. Emissions also occur

at multiples of the switching frequency

but at diminished amplitudes. The sim-

ple circuit in Figure 1 makes the switch-

ing converter operate over multiple fre-

quencies rather than one, thereby

reducing the time average at any one fre-

quency. This scheme effectively lowers

the peak emissions.

The circuit in Figure 1 is a self-starting

oscillator with an oscillation frequency of

approximately 500 Hz. When you apply

power, C 3 begins to charge up from 0V,

and the output of the TL331 comparator

is in a high-impedance state because its

noninverting input sees a higher voltage

than that of the inverting input. As C 3

charges, its voltage crosses the voltage ref-

erence of the R 1 -R 6 divider, and the com-

parator output trips to a low state. The

voltage on R 6 instantly drops to a lower

reference level because R 5 is now in par-

allel with R 6 .C 3 begins to discharge to-

ward this new reference level because R 3

is simultaneously in parallel with C 3 .The

cycle repeats after C 3 discharges to the

voltage on R 6 when the comparator out-

put reopens. You must carefully select the

components to ensure that the two volt-

age-reference states of R 6 are lower than

the upper and lower possible charge

states of C 3 . The circuit uses C 3 to adjust

the oscillator frequency; you should se-

lect C 3 to have a lower value than C 2 .The

oscillator’s frequency is approximately

equal to

92 EDN | MAY 27, 2004

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S WITCHING POWER SUPPLIES can be

design

ideas

5V BIAS

R 3

10k

C 1

0.1 F

R 1

10k

R 2

49.9k

IC 1

UCC3813

R T

13.7k

IC 1

C 2

1 F

COMP

REF

VCC

OUT

GND

TL331DBV

R 4

24.9k

Capacitor C 2 ac-couples the ramp

voltage of C 3 into the UCC3813’s oscil-

lator pin. The injected signal adds to the

charging current of C T during its posi-

tive portion (ac signal), thus increasing

the controller’s operating frequency.

During the injected signal’s

negative portion, some of C T ’s

charging current disappears, slowing

the controller’s operating frequency.

Figure 2 shows the effects of the inject-

ed signal on the charging of C T .R 4 con-

trols the magnitude of the current that

is injected. Reducing R 4 ’s value increas-

es the range, or spread, of the operat-

ing frequency around its nominal fixed

frequency. The injected signal’s oscilla-

tion frequency, which C 3 sets, controls

R 5

6.04k

R 6

4.99k

C 3

0.1

C T

330 pF

Figure 1

A low-frequency oscillator ramp, injected into the RC pin, modulates the supply’s switch-

ing frequency.

shows the before-and-after effects of

adding the frequency-shifting oscillator.

This design easily achieves a 10-

1 dB

the circuit below the power converter’s

low-frequency limits, or saturation of

magnetics may occur. This circuit demon-

strates a low-cost, small-area approach to

reducing conducted-EMI emissions.

A reduction with a 12-kHz

sweep window. A wider win-

dow further reduces EMI, but

the modulator frequency may

be noticeable in the converter’s

output ripple voltage. It is also

desirable to make the injected

ramp voltage as linear in shape

as possible to prevent the

switching converter from

spending excess time at its

switching-frequency limits. The

nonlinearity can result in an

EMI response with two

distinct frequencies. You

must take care not to operate

SEC

0.50V

10115 SWPS

SEC BWL

1 50 mV DC

2 50 mV DC

3 0.1V DC

4 0.5V DC

200 mSAMPLES/SEC

1 DC 1.39V

□

STOPPED

Figure 2

The external oscillator varies

the charging of the timing capacitor.

Figure 3

The EMI of the flyback converter

differs with and without external modulation.

Get just enough boost voltage

Kieran O’Malley, On Semiconductor, East Greenwich, RI

A DDING A CURRENT-MIRROR circuit to

V IN 14V

a typical boost circuit allows you to

select the amount of boost voltage

and to ensure a constant difference be-

tween the input and the output voltages

( Figure 1 ). This circuit is useful for high-

side-drive applications, in which a sim-

ple voltage doubler is unacceptable be-

cause of the voltage range of the

components involved or where the input

voltage can vary widely. You can also use

the circuit at the front end of a

power supply to ensure that the

PWM controller has enough voltage to

start correctly in low-input-voltage con-

L 1

C 1

22 F

SHUTDOWN

V OUT 24V

D 1

VOC

VSW

BC856BDWLT1

IC 1

CS5171

MBRS120T3

C 3

22 F

AGND PGND

VFB

Q 1A

Q 1B

C 2

0.01

R 2

10k

R 4

8.2k

Figure 1

R 1

4.7k

R 3

1.27k

Adding a current-mirror circuit to a boost circuit allows you to get just enough boost voltage.

94 EDN | MAY 27, 2004

www.edn.com

the frequency-sweep rate.

The differential EMI-current measure-

ment of Figure 3 (1 dB

design

ideas

ditions. The circuit maintains a 10V dif-

ference between V IN and V OUT ,but you

can easily change it to provide other volt-

ages. The PWM circuit in Figure 1 is the

CS5171 from On Semiconductor (www.

onsemi.com), but you can use the idea

with any boost circuit. The current-mir-

ror circuit, comprising the dual-pnp

transistor, Q 1 , and the associated resis-

tors, establishes a current that depends on

the voltage difference between V IN and

V OUT . The dual-pnp transistor has a V CEO

14V (nominal),

so you need V OUT to be 24V (nominal).

First, calculate a value for R 2 , thus estab-

lishing the reference current. If you select

a reference current of 1 mA, you obtain

resistor.

Q 1B mirrors the current and sets up the

feedback voltage to the PWM circuit. The

CS5171 has an internal voltage of 1.28V

(typical), so R 3 yields the correct feedback

voltage when the current flowing

through it is 1 mA. In this case, by select-

ing 1.27 k

for R 3 , you obtain an output

voltage of 24V. As V IN varies, V OUT tracks

it and maintains a 10V difference be-

tween the input and the output. R 4 helps

reduce the power dissipation in Q 1B .

Because the output voltage is not critical,

Processor’s PWM output controls LCD/LED driver

Joe Neubauer, Maxim Integrated Products, Sunnyvale, CA

output available from many micro-

processors is based on an internal 8-

or 16-bit counter and features a pro-

grammable duty cycle. It is suitable for

adjusting the output of an LCD driver

( Figure 1 ), a negative-voltage LCD driv-

er ( Figure 2 ), or a current-controlled

LED driver ( Figure 3 ). The circuit com-

prises simply the PWM source, capacitor

C, and resistors R D and R W . For CMOS

circuits, you calculate the open-circuit

output voltage as V CONT

voltage, V CONT :

V DD ,where

V CONT is the control circuit’s output volt-

age, D is the PWM duty cycle, and V DD is

the logic-supply voltage. The control cir-

cuit’s output im-

pedance is the sum

of the resistor values

R D and R W :R CONT

R D

where V REF is the reference voltage at the

feedback input.

Bear in mind that the initial charge on

filter capacitor C produces a turn-on

transient. The capacitor forms a time

constant with R CONT , which causes the

output to initialize at a voltage higher

than that intended. You can minimize

this overshoot by scaling the value of R D

as high as possible with respect to R 1 and

R 2 . As an alternative, the microprocessor

can disable the LCD until the PWM volt-

V IN

SWIN

MAIN

3.3V

300 mA

C 1

C 3

SDIG

3.3V

200 mA

R W . For the cir-

cuit of Figure 1 , the

output voltage,

V OUT , is a function

of the PWM average

REF

C 5

MAX1552

C 8

1.5V

200 mA

COR1

C 4

SDIG

OFF

ENSD

COR2

1.8V

20 mA

V IN

C 6

COR2

ENC2

OFF

R SENSE

C 9

LCD

ENLCD

LCD

20V

1 mA

L 1

0.1

OFF

D 1

MAIN

C 2

ADJ

DHI

R 3

R 4

C 7

DIGITAL

ADJUST

R 1

V OUT

MAX749

RESET

OUTPUT

LOW-BATTERY

OUTPUT

LFB

CTRL

DLOW

R 2

ON/OFF

GND

LBO

GND

CONNECTION FOR

PWM-CONTROLLED

LCD BIAS

Figure 2

R FB

C COMP

CONNECTION FOR

PWM-CONTROLLED

LCD BIAS

V DD

R W

R D

FROM

PROCESSOR

PWM OUTPUT

R W

R D

FROM

PROCESSOR

PWM OUTPUT

Figure 1

This simple circuit provides positive-output voltage LCD drive.

This configuration provides negative-output-voltage LCD drive.

96 EDN | MAY 27, 2004

www.edn.com

of 65V. In this case, V IN

you use a 10-k

T HE PWM (pulse-width-modulation)

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