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Power Management
Texas Instruments Incorporated
Designing DC/DC converters based on
SEPIC topology
By Jeff Falin
Senior Applications Engineer
Introduction
The single-ended primary-inductance converter (SEPIC)
is a DC/DC-converter topology that provides a positive
regulated output voltage from an input voltage that varies
from above to below the output voltage. This type of con-
version is handy when the designer uses voltages (e.g.,
12 V) from an unregulated input power supply such as a
low-cost wall wart. Unfortunately, the SEPIC topology is
difficult to understand and requires two inductors, making
the power-supply footprint quite large. Recently, several
inductor manufacturers began selling off-the-shelf coupled
inductors in a single package at a cost only slightly higher
than that of the comparable single inductor. The coupled
inductor not only provides a smaller footprint but also, to
get the same inductor ripple current, requires only half
the inductance required for a SEPIC with two separate
inductors. This article explains how to design a SEPIC
converter with a coupled inductor.
Basic operation
Figure 1 shows a simple circuit diagram of a SEPIC con-
verter, consisting of an input capacitor, C
IN
; an output
capacitor, C
OUT
; coupled inductors L1a and L1b; an AC
coupling capacitor, C
P
;apowerFET,Q1;andadiode,D1.
Figure 2 shows the SEPIC operating in continuous con-
ductionmode(CCM).Q1isoninthetopcircuitandoffin
the bottom circuit.
To understand the voltages at the various circuit nodes,
itisimportanttoanalyzethecircuitatDCwhenQ1isoff
and not switching. During steady-state CCM, pulse-width-
modulation (PWM) operation, and neglecting ripple voltage,
Figure 1. Simple circuit diagram of
SEPIC converter
L1a
C
P
D1
V
IN
V
OUT
Q1
C
IN
L1b
C
OUT
Figure 2. SEPIC during CCM operation when Q1 is
on (top) and off (bottom)
+
–
V
L1a
L1a
C
P
+–
V
IN
V
OUT
+
I
L1a
+
I
L1b
C
IN
L1b
V
L1b
C
OUT
–
–
+
–
V
L1a
L1a
D1
C
P
+–
V
IN
V
OUT
+
I
L1a
+
I
L1b
C
IN
C
OUT
L1b
V
L1b
–
–
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High-Performance Analog Products
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Analog Applications Journal
Texas Instruments Incorporated
Power Management
capacitor C
P
is charged to the input voltage,
V
IN
. Knowing this, we can easily determine
the voltages as shown in Figure 3.
WhenQ1isoff,thevoltageacrossL1b
must be V
OUT
. Since C
IN
is charged to V
IN
,
thevoltageacrossQ1whenQ1isoffisV
IN
+
V
OUT
, so the voltage across L1a is V
OUT
. When
Q1ison,capacitorC
P
, charged to V
IN
, is con-
nected in parallel with L1b, so the voltage
across L1b is –V
IN
.
The currents flowing through various cir-
cuit components are shown in Figure 4. When
Q1ison,energyisbeingstoredinL1afrom
the input and in L1b from C
P
.WhenQ1turns
off, L1a’s current continues to flow through
C
P
and D1, and into C
OUT
and the load. Both
C
OUT
and C
P
get recharged so that they can
provide the load current and charge L1b,
respectively,whenQ1turnsbackon.
Duty cycle
Assuming 100% efficiency, the duty cycle, D,
for a SEPIC converter operating in CCM is
given by
Figure 3. SEPIC component voltages during CCM
+
V
V
IN(max)
OUT
Q1
ON
Q1
OFF
V
Q1
V
OUT
V
L1b
–V
IN
V
OUT
V
L1a
V
IN
(V
< V)
IN
OUT
V
IN
V
L1a
V
OUT
(V
> V)
IN
OUT
Figure 4. SEPIC component currents during CCM
V V
VV
+
OUT WD
IN OUT WD
D
=
,
(1)
T
S
+
+
V
V
+ V
IN
OUT
where V
FWD
is the forward voltage drop of the
Schottky diode. This can be rewritten as
V
Q1
D × T
S
(1–D) × T
S
D
D
V
+
V
I
OUT WD
IN
IN
OUT
=
=
.
(2)
I
Q1(Peak)
1−
V
I
I+ l
IN
OUT
l
Q1
D(max) occurs at V
IN(min)
, and D(min) occurs
at V
IN(max)
.
Selecting passive components
OneofthefirststepsindesigninganyPWM
switching regulator is to decide how much
inductor ripple current, ∆I
L
, to allow. Too
much increases EMI, while too little may
result in unstable PWM operation. A rule of
thumb is to use 20 to 40% of the input cur-
rent, as computed with the power-balance
equation,
I+ l
IN
OUT
l
D1
I
IN
l
C
P
–I
OUT
I
I
IN
IN
∆I
= × = ×
30
%
30
% ′.
I
(3)
l
L1a
η
L
IN
In this equation, I
IN
from Equation 2 is divided
by the estimated worst-case efficiency, η, at
V
IN(min)
and I
OUT(max)
for a more accurate
estimate of the input current, I
IN
′.
In an ideal, tightly coupled inductor, with
each inductor having the same number of
windings on a single core, the mutual induc-
tance forces the ripple current to be split
equally between the two coupled inductors.
In a real coupled inductor, the inductors do
I
OUT
I
L1b
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High-Performance Analog Products
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Texas Instruments Incorporated
not have equal inductance and the ripple currents will not
be exactly equal.
Regardless, for a desired ripple-current
value, the inductance required in a coupled inductor is
estimated to be half of what would be needed if there
were two separate inductors, as shown in Equation 4:
capacitance, but not too much ESR, to meet the applica-
tion’s requirement for output voltage ripple, ∆V
RPL
:
I
×
×
D
(max)
OUT
OUT W
∆V
≤
RPL
C
f
(min)
(6)
+×
ESRI
+
I
V
×
D
(max)
LaPeak
1
(
)
LbPeak
1
(
)
1
2
IN
(min)
La
1
(min)
=
Lb
1
(min)
= ×
(4)
∆
I
×
f
If very low-ESR (e.g., ceramic) output capacitors are used,
the ESR can be ignored and the equation reduces to
L W
(min)
To account for load transients, the coupled inductor’s
saturation current rating needs to be at least 20% higher
than the steady-state peak current in the high-side induc-
tor, as computed in Equation 5:
I D
Vf
×
×
(max)
OUT
RPL W
(7)
C
≥
,
OUT
∆
(min)
where f
SW(min)
is the minimum switching frequency. A
minimum capacitance limit may be necessary to meet the
application’s load-transient requirement.
The output capacitor must have an RMS current rating
greater than the capacitor’s RMS current, as computed in
Equation 8:
∆
I
30
2
%
L
(5)
I
=+=
I
′
I
′
1
+
LaPeak
1
(
)
IN
IN
2
Note that I
L1b(Peak)
= I
OUT
+ ∆I
L
/2, which is less than
I
L1a(Peak)
.
Figure 5 breaks down the capacitor ripple voltage as
relatedtotheoutput-capacitorcurrent.WhenQ1ison,
the output capacitor must provide the load current.
Therefore, the output capacitor must have at least enough
D
D
(max)
(max)
I
=
I
×
(8)
C
OUT
(
MS OUT
)
1
−
Figure 5. Ripple voltage of output capacitor
T
S
I
IN
I
C
OUT
D × T
S
(1–D) × T
S
–I
OUT
V×
(
I
)
+ I
–I
ESR
L1a
L1b
OUT
∆
V
RPL_ESR
V× I
ESR
OUT
∆
V
RPL_C
OUT
V=
V
∆
+
∆
V
∆
RPL
RPL_ESR
RPL_C
OUT
∆
V
RPL
V
OUT_AC
20
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Analog Applications Journal
Texas Instruments Incorporated
Power Management
The input capacitor sees fairly low ripple currents due
to the input inductor. Like a boost converter, the input-
current waveform is continuous and triangular; therefore,
the input capacitor needs the RMS current rating,
The output diode must be able to handle the same peak
currentasQ1,I
Q1(Peak)
. The diode must also be able to
withstandareversevoltagegreaterthanQ1’smaximum
voltage (V
IN[max]
+ V
OUT
+ V
FWD
) to account for transients
and ringing. Since the average diode current is the output
current, the diode’s package must be capable of dissipat-
ing up to P
D_D1
= I
OUT
× V
FWD
.
Design example
A DC/DC converter is needed that can provide 12 V at
300 mA (maximum) with 90% efficiency from an input
voltage ranging from 9 to 15 V. We select the TPS61170,
which has a 38-V switch, a minimum switch-current limit of
0.96 A, and a 1.2-MHz nominal (1.0-MHz minimum) switch-
ing frequency. The maximum output voltage ripple allowed
is 100 mV
PP
. The maximum ambient temperature is 70ºC,
and we will use a high-K board. In Reference 1, Ray Ridley
explains how to compensate the control loop at the link.
Table 1 summarizes the computations using the equa-
tions given earlier. Equations 8 through 11 are not shown
because ceramic capacitors with low ESR, high RMS cur-
rent ratings, and the appropriate voltage ratings were
used. Figure 6 shows the schematic. Figure 7 shows the
design’sefficiencywithaCoiltronicsDRQ73inductorand
a Wurth 744877220. Figure 8 shows the device operation
in deep CCM.
References
1. Ray Ridley. (Nov. 2006). Analyzing the SEPIC
converter.
Power Systems Design Europe
[Online].
Available:
http://www.powersystemsdesign.com/design_
tips_nov06.pdf
2. Robert W. Erickson and Dragan Maksimovic,
Fundamentals of Power Electronics
, 2nd ed. (New
York: Springer Science+Business Media LLC, 2001).
3. John Betten and Robert Kollman. (Jan. 25, 2006). No
need to fear: SEPIC outperforms the flyback.
Planet
Analog
[Online].Available:
http://www.planetanalog.com/
showArticle.jhtml?articleID=177103753
Related Web sites
power.ti.com
www.ti.com/sc/device/TPS61170
=
∆
12
I
L
I
.
(9)
CRMS
IN
(
)
The coupling capacitor, C
P
, sees large RMS current rela-
tive to the output power:
=×
−
1
(max)
(max)
D
(10)
I
I
′
CRMS
P
(
)
IN
D
From Figure 3, the maximum voltage across C
P
is
V
Q1(max)
– V
L1b(max)
= V
IN
+ V
OUT
– V
OUT
= V
IN
.
The ripple across C
P
is
I
D
Cf
×
(max)
.
OUT
P W
∆V
=
(11)
C
×
P
Selecting active components
ThepowerMOSFET,Q1,mustbecarefullyselectedso
that it can handle the peak voltage and currents while
minimizing power-dissipation losses. The power FET’s
current rating (or current limit for a converter with an
integrated FET) will determine the SEPIC converter’s
maximum output current.
AsshowninFigure3,Q1seesamaximumvoltageof
V
IN(max)
+ V
OUT
.AsshowninFigure4,Q1musthavea
peak-current rating of
I
=
I
+
I
=+ +
I
′
I
∆
I
.
(12)
QPeak
1
(
)
L aPeak
1
(
)
LbPeak
1
(
)
IN UT
L
At the ambient temperature of interest, the FET’s power-
dissipation rating must be greater than the sum of the
conductive losses (a function of the FET’s r
DS[on]
) and the
switching losses (a function of the FET’s gate charge) as
given in Equation 13:
2
P
=
I
×
r
×
D
(max)
+
I
DQ QRMS
_
1
1
(
)
DS on
(
)
QPeak
1
(
)
(13)
t
+
t
Rise
Fall
×
×
V
+
V
+
V
×
f
,
IN
(min)
OUT W
D
SW
2
where t
Rise
istherisetimeonthegateofQ1andcanbe
computedasQ1’sgate-to-draincharge,Q
GD
, divided by the
converter’s gate-drive current, I
DRV
.Q1’sRMScurrentis
I
D
′
IN
(14)
I
=
.
QRMS
1(
)
(max)
21
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High-Performance Analog Products
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Table 1. Computations for SEPIC design example
DESIGN EQUATION
COMPUTATION
SELECTED COMPONENT/RATING
Passive Components
12 05
129
V V
VV
+
++
=
.
(1)
D
(max)
=
058
.
N/A
.
5
V
30% =
0.3 A12 V
9 V
×
×
LI
=
′
×
∆
I
×
30% =0.44 A
×
30% =0.13 A
(2) and (3)
N/A
90%
1
2
9 V0.58
0.13 A1 MHz
=20.1 µH
×
×
L1a = L1b =
×
(4)
Coiltronics DRQ73: 22 µH, 1.6 A, and 110 m
W
= 0.44 A +
30%
2
×
I
=0.51A
(5)
L1a(Peak)
0.3 A .58
0.1V
×
×
C
OUT
1 MHz
=1.74 µF
(7)
4.7-µF, 25-V X5R ceramic
Active Components
(12)
I
= 0.44 A+0.3 A+0.13 A=+0.87 A
Q1(Peak)
=
0.44 A
0.58
I
=0.58 A
(14)
TPS61170 with 0.96-A-rated switch. Capable
of dissipating 825 mW at 70ºC.
Q1(RMS)
2
×
P
(0.58 A)
0.3
Ω
×
0.58 +0.87 A
D_Q1
(13)
×
(9 V+12 V+0.5 V)
× ×
10 ns
1
MHz=246 mW
P
0.3 A .5 V=150 mW
×
—
MBA140: 1 A, 40 V
D_D1
Figure 6. SEPIC design with 9- to 15-V V
IN
and 12-V V
OUT
at 300 mA
C4
1 µF
L1a
22 µH
V=
12 V at 300 mA
V=
9 to 15 V
OUT
IN
D1
C
4.7 µF
L1b
22 µH
C
4.7 µF
IN
OUT
R1
87.6 k
Ω
TPS61170
VIN
SW
CTRL
FB
4.99 k
Ω
R2
10 k
Ω
COMP
GND
C3
22 nF
22
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Analog Applications Journal
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