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Texas Instruments Incorporated
Amplifiers: Op Amps
Interfacing op amps to high-speed DACs,
Part 2: Current-sourcing DACs
By Jim Karki
Member, Technical Staff, High-Performance Analog
Introduction
Most high-speed DACs are current-steering DACs that are
designed with complementary outputs that either source
or sink current. Part 1 (see Reference 1) of this three-part
article series discussed the interface between a current-
sinking DAC and an op amp. This article, Part 2, discusses
the interface between a current-sourcing DAC and an op
amp. This interface allows the designer to use the full
compliance voltage range of the DAC. Part 3, which will
appear in a future issue of the Analog Applications
Journal , will discuss interfacing a current-sourcing DAC
and an op amp by using the more popular configuration
that simply terminates to ground. This article series
focuses on using high-speed DACs in end equipment that
requires DC coupling, like signal generators with frequency
bandwidths of up to 100 MHz and a single-ended output.
In these cases, high-speed op amps can provide a good
solution for converting the complementary-current output
from a high-speed DAC to a voltage that can drive the
signal output.
It is assumed that the reader is familiar with the opera-
tion of complementary-current-steering DACs. If further
information is needed, please see Reference 1 for an over-
view. The design approach for Part 2 is the same as for
Part 1, except that a current-sourcing DAC was used to
derive the design equations instead of the current-sinking
DAC used in Part 1. Because of this, about half of the
equations are the same and about half are modified.
Architecture and compliance voltage of current-
sourcing DACs
Figure11showsasimplifiedexampleofaPMOScurrent
source and lists a few devices that use it. The compliance
voltage shown is the voltage range at the DAC outputs
within which a device will perform as specified. Higher
Figure 11. Simplified PMOS current source
PMOS
DD
AV
Example Devices:
DAC902, DAC2902,
DAC5662, DAC5674
Current-
Source
Cascodes
Switches
Output
Compliance Voltage:
1.0 V to +1.25 V
I OUT1
I OUT 2
–
voltages tend to shut down the outputs, and lower voltages
have the potential to cause breakdown. Both of these
should be avoided to provide the best performance and
long term-reliability.
Generally the output is terminated via some impedance
to ground. This impedance supplies a current path needed
for the array, and the voltage drop across the same imped-
ance can be used as a voltage output. The impedance can
be constructed in various ways; it can be a simple resistor
divider, a transformer-coupled impedance, or an active cir-
cuit like an op amp. This article focuses on the interface to
an op amp.
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4Q 2009
High-Performance Analog Products
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Amplifiers: Op Amps
Texas Instruments Incorporated
Op amp interface
A proposed op amp interface is shown in
Figure 12. This circuit will provide biasing
of the DAC outputs, convert the DAC cur-
rents to voltages, and provide a single-
ended output voltage. The op amp is the
active amplifier element for the circuit and
is configured as a difference amplifier.
•I DAC+ and I DAC – are the current outputs
from the DAC.
•R 2 and R 3 are input resistors to the posi-
tive input of the op amp.
•R G and R F are the main gain-setting resis-
tors for the op amp.
•R X , R 1 , R Y , and R 4 provide bias and imped-
ance termination for the DAC outputs.
•V DAC+ and V DAC – are the voltages at the
outputs of the DAC.
•V p and V n are the input terminals of the
op amp.
•V S+ and V S– are the power supplies to the op amp.
Proper component selection will provide the impedance
required to maintain voltage compliance with maximum
amplitude and balance for the best performance. The
analysis of this circuit follows from Part 1 with only minor
changes due to the change in polarity of the DAC current
(sourcing versus sinking) and the change in compliance
voltage range around ground instead of AV DD . The circuit
in Figure 12 enables the designer to use the maximum
compliance voltage range of the DAC.
The motivation for this interface design is to balance the
input voltages to the difference-amplifier circuit to sup-
press second-order harmonics, and little impact is expected
on third-order harmonics. Also, because it allows higher
voltage swings at the DAC output than simple termination
to ground, the gain of the op amp will be lower given the
same output-voltage requirement.
Analysis of positive side
Figure 13 shows the analysis circuit for the positive side.
The node equation at the V DAC+ output is the same as in
Part 1 but with a change in the polarity of I DAC+ :
V
Figure 12. Proposed circuit for an op amp interface
AV DD
DAC Bias Network
V REF
V DAC+
Input Resistors
to Positive Input
of Op Amp
I DAC+
R X
R 2
V S+
R 1
Z DAC+
R 3
V p
+
AV DD
Op Amp
V OUT
V n
V REF
–
V DAC –
I DAC –
R Y
V S–
R G
R F
Current-
Sourcing
DAC
R 4
Z DAC–
Op Amp Gain Resistors
criteria. The following assumptions are made in this article:
1. The DAC output current, I DAC+ , and the voltage swing,
V DAC+ , are defined by the designer to set a target value
for Z DAC+ .
2. An existing circuit voltage or other known voltage is
used for V REF .
3. In a difference amplifier, R 3 /R 2 needs to equal R F /R G to
balance the gain of the amplifier.*
4. The equations will be solved for the condition where the
DAC current on the positive side is zero (I DAC+ = 0 mA).
This in turn will set the DAC voltage on the positive side
to its minimum value, V DAC+ = V DAC+(min) . Note that
this value is different from that of the current-sinking
DAC in Part 1, where setting I DAC+ = 0 mA led to
V DAC+ = V DAC+(max) .
* Note that in a voltage-feedback op amp, it is desirable to make the imped-
ance at V p equal to that at V n in order to cancel voltage offset caused by the
input bias current. In a current-feedback op amp, the input bias currents are
not correlated; so it is acceptable not to balance these impedances, but it
may be desirable to minimize them.
−
V
V
V
RR I
Figure 13. Positive side of analysis circuit
DAC
+
REF
DAC
+
DAC
+
(20)
+
+
−
=
0
DAC
+
R
R
+
X
1
2
3
AV DD
V REF
The equation for the DAC output impedance stays
the same:
Z
Z DAC+
I DAC+
R X
I ~ 0
(21)
To solve Equations 20 and 21, which are simultaneous
equations with more variables than equations, the designer
must choose or identify values based on other design
+ =
R
||
RRR
|| (
+
)
R 2
DAC
X
1
2
3
V p
V DAC+
R 3
R 1
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4Q 2009
Analog Applications Journal
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Texas Instruments Incorporated
Amplifiers: Op Amps
With these constraints, algebra and simultaneous-equation
techniques can be applied to Equations 20 and 21 to solve
for 1/R 1 :
1
Figure 14. Negative side of analysis circuit
AV DD
V R EF
Z DAC –
1
1
=
−
(22)
R
RR
+
1
V n
1
2
3
I DAC–
R Y
1
+
V
Z
R G
R F
DAC
+
REF
DAC
−
1
V OUT
V
+(min)
V DAC–
R 4
The known value for R 1 can be substituted into Equation
21, which can then be rearranged to find 1/R X . The result
is exactly the same as in Part 1:
1
1
1
1
=
− −
(23)
RZ
RRR
+
X AC
+
1
2
3
side to its minimum value, V DAC – = V DAC –(min) , and sets
the DAC voltage on the positive side to its maximum
value, V DAC+ = V DAC+(max) . The value of 1/R 4 can then be
used to find 1/R Y :
Analysis of negative side
Figure 14 shows the analysis circuit for the negative side.
The node equation at the V DAC – output is the same as in
Part 1 except for the DAC current’s change in polarity:
V
R
RR
3
Z
×
α
DAC
+
−
V
V
V V
RR
−
+
2
3
DAC
−
REF
DAC
−
DAC
−
n
+
+
−
I
=
0
(24)
1
−
DAC
−
R
R
+
1
R
11
Y
4
G
3
G
DAC
=
−+
(28)
R
Z
R
R
The equation for the DAC output impedance stays
the same:
Y
−
4
G
Note that α, the multiplication factor from V p to V n , in
essence expresses the difference between the input pins.
In a voltage-feedback amplifier, α is set by the loop gain of
the amplifier. In a current-feedback amplifier, α is the gain
of the input buffer between the inputs. All that aside, α is
typically close enough to 1 that it can simply be removed
from the calculation.
Calculating output voltage
Superposition can be used to write equations for the sepa-
rate terms referred to V OUT . These equations are the same
as those in Part 1. The difference is that now the DAC only
sources current, which is by convention positive current
flow, making the direction of the op amp’s output-voltage
swing match that of the DAC. In other words, when the
DAC is sourcing current on the positive side, the output of
the op amp tends to swing positive, and when the DAC is
sourcing current on the negative side, the output of the
op amp tends to swing negative. This means that in the
following equations, I DAC+ and I DAC – are always positive
or zero.
V
I
DAC
DAC
−
−
Z
=
(25)
DAC
−
With substitution and rearrangement,
R
RR
3
VV
=
×
,
p
AC
+
+
2
3
and V n = αV p can be used to rewrite Equation 25 as
1
1
111
=
× + +
. (26)
Z
RRR
R
RR
DAC
−
Y
4
G
3
Z
×
α
DAC
+
+
2
3
1
−
R
G
Usingthesamesubstitutionsandgeneraldesigncon-
straints used on the positive side to drive values for Z DAC – ,
V REF , and R G , simultaneous-equation techniques can be
applied to Equations 24 and 26 to solve for 1/R 4 (Equation
27 below). Note that the equations are solved for the con-
dition where the DAC current on the negative side is zero:
I DAC – = 0 mA. This sets the DAC voltage on the negative
R
RR
3
Z
×
α
DAC
+
R
RR
+
3
2
3
V
×
α
 −
V
1
−
DAC
+
(max)
DAC
−
(min)
+
1
R
2
3
G
DAC
−
1
+
VV
−
R
Z
1
G
REF AC
−
(min)
−
=
(27)
V
R
4
DAC
−
(min
)
(min)
+
1
VV
REF AC
−
−
25
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4Q 2009
High-Performance Analog Products
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Amplifiers: Op Amps
Texas Instruments Incorporated
The output-referred DC bias from the positive side is
RR
RR RRRR
R
RRR
×
F
GY
13
V
×
V
=+ +
1
.
OUTV
_
REF
(
) +
(
)
||
+
+
2 +
R 3
pDC
()
4
12 3
X
1
The output-referred DAC signal from the positive side is
R
RRR
RRR
×
X
13
F
GY
V
=+ +
1
I
×
.
DAC
+
OUTV
_
(
)
(
)
||
RR
++
RR R
+
R
pDAC
(
)
4
X
1
1
X
2
3
The output-referred DC bias from the negative side is
R
RR
R
RRR
4
F
GY
V
=−
V
×
×
.
OUTV
_
REF
+
+
||
nDC
()
Y
4
4
The output-referred DAC signal from the negative side is
RRR
Y
4
F
V
=−
I
×
.
OUTV
_
DAC
−
RR
+
RR
+
RR
nDAC
(
)
Y
4
G
4
YG
Adding these four equations provides an expression for V OUT :
V
=
V
+
V
+
V
+
V
(29)
OUT UT V
_
OUT V
_
OUT V
_
OUT V
_
pDC
()
p DAC
(
)
n DC
()
nDAC
(
)
If it is assumed that I DAC = I DAC+ – I DAC – , Z = Z DAC+ =
Z DAC – , and R F /R G = R 3 /R 2 , the DC component of the DAC
outputs will cancel and the AC signal’s gain equation from
the DAC output current to the voltage output of the op
amp can be simplified and written as
V
I
require V REF to be a negative voltage. The DAC full-scale
output is set to 20 mA. To get a 5-V PP , DC-coupled single-
ended output signal, the circuit shown in Figure 12 can be
used. Since a ±5-V power supply is being used for the op
amp, it is convenient to make V REF = –5 V. Given that
I DAC± = 20 mA and V DAC± = 2.25 V PP , the target impedance,
Z DAC± , can be calculated to equal 112.5 Ω.
With the starting design constraints given earlier, the
Texas Instruments THS3095 current-feedback op amp is
selected as the amplifier, where R 3 = R F = 750 Ω. The gain
from V DAC± to the output is given by the resistor ratios
R F /R G = R 3 /R 2 , so R G can be calculated as
R
R
OUT
DAC
F
G
=×
2
Z
.
(30)
Design example and simulation
For an example of how to proceed with the design, assume
thatthePMOSDACnotedearlier,withacompliancevolt-
age ranging from –1.0 V to +1.25 V, is being used. Also
assume that the full compliance voltage range will be used
to maximize the DAC output voltage, which in turn will
minimize the gain required from the op amp and will
V
V
2
(
2.25 V
5 V
)
DAC
OUT
±
RRR
==×
=
750
Ω
×
=
675
Ω
.
G
2
F
The nearest standard 1% value, 681 Ω, should be used.
26
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4Q 2009
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Texas Instruments Incorporated
Amplifiers: Op Amps
Equations 22, 23, 27, and 28 can be used to find, respectively, R 1 , R X , R 4 , and R Y :
1
1
R
=
=
=
155.95
Ω
1
1
1
1
1
−
−
RR
+
681
ΩΩ
+
750
1
1
2
3
112.50 Ω + −
−
Z
1
+
1
DAC
+
V
5
1
V
V
REF
DAC
−
1
−
1
V
+(min)
1
1
R
=
=
=
562
.5 Ω
X
1
1
1
1
1
1
−− +
−
−
Z
R
RR
112.5
Ω
155.95
Ω
681
ΩΩ
+
750
DAC
+
1
2
3
V
VV
DAC
REF AC
−
(min)
(min)
+
1
−
−
R
=
4
R
RR
3
Z
×
α
DAC
+
+
R
RR
2
3
α 3
2
V
×
−
V
1
−

DAC
+
(max)
DAC
−
(min)
+
R
1
3
G
DAC
+
−
1
Z
VV
−
R
−
REF AC
−
(min)
G
−
−+ +
1
51 1
V
V
V
=
=
206.84
Ω
750
Ω
Ω 0
112.5
Ω
××
1
750
Ω
ΩΩ
681
+
75
Ω
−
1.25
+
1
1
V
××
1
V

1
681
68 1
112.5
Ω
Ω
681
+
750
+
−
1
−+
51
V
V
Ω
1
1
R
=
=
=
55
0.58 Ω
Y
750
Ω
ΩΩ
R
RR
3
112.5 Ω×××
1
Z
×
α
681
+
750
DAC
+
+
1
−
2
3
1
1
1
−
681
112.5
Ω
Ω
−
+
R
11
G
DAC
206.84
Ω
681
Ω
− +
Z
R
R
−
4
G
The nearest standard 1% values should be used:
R 1 = 154 Ω, R X = 562 Ω, R 4 = 205 Ω, and R Y = 549 Ω.
These equations are easily solved when set up in a
spreadsheet. To see an example Excel ® worksheet, go to
the WinZip ® directory online (or click Save to download
the WinZip file for offline use). Then open the file DAC_
Source_to_Op_Amp_Wksht.xlsandselectthe“DAC
SourcetoOpAmp,NoFilter”worksheettab.
SPICE simulation is a great way to validate the design.
To see a TINA-TI™ simulation of the circuit in this exam-
ple,goto http://www.ti.com/lit/zip/slyt360 andclickOpen
to view the WinZip directory online (or click Save to
download the WinZip file for offline use). If you have the
TINA-TI software installed, you can open the file DAC_
Source_to_Op_Amp_No_Filter.TSCtoviewtheexample.
To download and install the free TINA-TI software, visit
www.ti.com/tina-ti and click the Download button.
27
Analog Applications Journal
4Q 2009
High-Performance Analog Products
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