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Texas Instruments Incorporated
Data Acquisition
Impact of sampling-clock spurs on
ADC performance
By Thomas Neu
Analog Field Applications Engineer
Introduction
As modern, high-speed analog-to-digital
converters (ADCs) push the spurious-free
dynamic range (SFDR) beyond the 100-dB
barrier, the demand for a high-quality sam-
pling clock has become greater than ever.
Traditionally, system engineers focused
mainly on the clock quality when they were
trading off the signal-to-noise ratio (SNR)
against the input-signal frequency in under-
sampling applications. As tougher system
requirements such as multicarrier GSM
emerge and are starting to demand dynamic
ranges in excess of 80 dB over a wide band-
width, system designers try to eliminate any
possible SFDR degradation, such as the spur
feedthrough from a distorted sampling clock.
Spurs on the sampling clock as low as
–90 dBc can significantly impact the SFDR
of the data converter. These low-level spurs
can be very difficult to track down because
they can have a variety of different origins.
They can be generated from crosstalk with
an adjacent digital circuit that occurs due to
layout constraints, or they can occur simply
because the clock source is not properly
filtered. An example of improper filtering is
shown in Figure 1, which compares two
LVDS outputs of the Texas Instruments (TI) CDCE72010,
one unfiltered and one with a band-pass filter. The spur
reduction of the filtered output is clearly visible.
This article will discuss how spurs on the sampling
clock get translated into the output spectrum of the data
converter. It will also investigate how the spur amplitude
changes with different input frequencies. More and more
system designers are moving to an undersampling archi-
tecture, and the spur amplitude is highly dependent upon
input frequency, as will be shown later. This article will
also show how to estimate the SNR degradation caused by
the sampling-clock spurs.
Sampling theory
The spurs that result from sampling a data converter with
a distorted clock are best described by the relationship of
their frequency and amplitude components to the same
Figure 1. Phase noise of CDCE72010’s filtered
and unfiltered LVDS outputs
–100
–110
Unfiltered, Spur
at 27-MHz Offset
–120
–130
Unfiltered, Spur
at 3-MHz Offset
–140
–150
–160
With Band-Pass Filter
–170
–180
100
1 k
10 k 100 k
Frequency (Hz)
1 M
10 M
components of the sampled input signal. In order to derive
that relationship, one has to start with the basic sampling
theory. Let’s consider the setup shown in Figure 2, where
the input signal is
xt
()
=×w
A
sin(
t
),
IN
IN
and the clock input with a spurious component is
yt
=× +w w
The quality of the sampling clock can easily be evaluated
with a phase-noise analyzer. It displays the clock’s phase
noise versus frequency offset from the carrier, which is
very helpful when the clock jitter is calculated to determine
the SNR of the receiver. The phase-noise plot displays any
spurious component on the clock signal, referencing its
frequency offset and spur amplitude, S
X
, to the main signal.
If the amplitude is normalized in dBc/Hz, care must be
()
A
sin(
t
)
B
sin( .
t
CLK
S
5
Analog Applications Journal
3Q 2009
www.ti.com/aaj
High-Performance Analog Products
Data Acquisition
Texas Instruments Incorporated
Figure 2. Setup with input signal, clock, and clock spur
–100
Clock Input with
Spur Present
Amplitude and
Frequency Offset of Spur
A
–120
–140
Phase-Noise
Measurement
B
–160
Clean Input Signal
A
IN
f
CLK
f
S
–160
Clock
–180
100
1 k
10 k 100 k
Frequency (Hz)
1 M
10 M
Input
Digital Output
ADC
f
IN
FFT Processing
Spur
Amplitude
(dBc)
FFT Analysis
mm
f
IN
f
IN
f
S1
f
S2
f
S1
f
S2
taken to extract it with the resolution bandwidth of the instrument in that measurement:
Amplitude (dBc) = S
X
(dBc/Hz) + 10log(Resolution Bandwidth)
Due to the presence of the spur, the original sampling instant, or zero crossing of the clock, has shifted slightly by ∆T.
Now the sampling instant, y(t) = 0, can be solved for:
yt
()
=×
A
sin[
w
(
t
+ + ×
∆
TB
)]
sin[(
w
t
+
∆
T
)]
=
0
CLK
S
()
=×
yt
A
sin(
w
t
)cos(
×
w
∆
TA
)
+ ×
cos(
w
t
)sin(
×
w
∆
T
)
+×
B
s
in()cos(
w
t
×
w
∆
T
)
+ ×
B
cos()sin(
w
t
×
w
∆ 0
T
)
=
CLK
CLK
CLK
CLK
S
S
S
S
Assuming that B << A and ∆T ≈ 0 results in:
cos(
w
∆
T
)
≈
1
sin(
w
∆
T
)
≈
w
∆
T
CLK
CLK
CLK
cos(
w
∆
T
)
≈
1
sin(
w
∆
T
)
≈
w
∆
T
S
S
S
The ideal sampling instant is t = 0, hence:
sin(
w
t
)
=
0
cos(
w
t
)
=
1
cos(
w
t
)
=
1
CLK
CLK
S
Substituting these results into y(t) = 0 produces:
yt A
()
=×
sin(
ω
t
)cos(
×
ω
∆
TA t
)
+ ×
cos(
ω
)sin(
×
ω
∆
T
)
+×
B
s
in()cos(
ω
t
×
ω
∆
T
)
+ ×
B
cos( )sin(
ω
t
×
ω
∆
0
T
)
=
CLK
CLK
CLK
CLK
S
S
S
S
0
1
1
ω
CLK
∆
T
1
1
ω
S
∆
T
()
=×
yt
A
w
∆
T
+×
B
sin(
w
t
)
+× =
BT
w
∆
0
CLK
S
S
B
×
sin(
w
t
)
=−
×
B
sin(
w
t
)
.
S
S
CLK
Then T can be solved for:
∆
∆T
=−
.
Assuming that A >> B results in ∆T
A
×
w
+ ×
B
w
A
×
w
CLK
S
Next, the input signal, x(t) = A
IN
×sin(w
IN
t), is sampled at the zero crossing, t + ∆T, of the non-ideal clock:
xt A
×
( )
()
=×
sin(
ω
T
)
=×
A
sin
ω
(
t TA
+
∆
)
=× ×
sin( )cos(
ω
t
ω
∆
TA t
)
+×
cos(
ω
) sin
ω
∆
T
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
ω
IN
∆
T
6
High-Performance Analog Products
www.ti.com/aaj
3Q 2009
Analog Applications Journal
Texas Instruments Incorporated
Data Acquisition
This results in xt
()
=× +×
A
sin(
ω
t
)
A
cos(
ω
t
)
×
ω∆
T
.
IN
IN
IN
IN
IN
Ideal Sample
Error Sample
Focusing on the error sample and substituting ∆T produces:
=××
−×
×
B
sin(
ω
t
)
cos(
B
1
2
{
}
S
CLK
xt
()
A
ω
ω
t
)
=××
×
A
ω
×
sin(
−+ ×
ωω
)
t
+ − − ×
sin (
ωω
)
t
IN
IN
IN
IN
IN
SIN
S
IN
A
ω
A
ω
CLK
Scale Factor of
Spur Amplitude
Two Frequency Products:
–
ω
S
+
ω
IN
and –
ω
S
–
ω
IN
Therefore, it can be observed that each spurious component of the sampling clock generates two spurs, S1 and S2, in the
data converter with amplitude and frequencies relative to the input signal as follows.
w
w
f
B
A
B
A
IN
CLK
IN
CLK
S1 and S2 amplitude:
×
×
=×
×
or in terms of decibels
,
,
2
2
f
f
IN
CLK
=−+
BA
20
log
.
2×
f
S1 and S2 frequencies:
f
=− −
=− +
The resulting spurs can be shifted by one clock period, 2p/T = f
CLK
, and considering f
S
– f
CLK
= m yields:
f
f
f
S
1
S
IN
f
f
f
S
2
S
IN
1
=− −+ =− + − =− − + =− +=+
f
f
f
f
f
f
(
f
f
f
)
(
f
mf
)
m
S
S
IN
CLKIN
LK
S
IN
LK
S
IN
IN
f
2
=− ++ =+ + − =−
f
f
f
f
f
f
f
m
S
S
IN
CLKIN
LK
SIN
These equations show that the frequencies of the gener-
ated spurs will be centered around the input signal and
offset by the distance m, which is the difference between
the clock frequency and the clock-spur frequency. The
amplitude of the generated spurs, on the other hand, is
highly dependent upon the input frequency. For every
doubling of the input frequency (e.g., f
IN
= 20 MHz versus
f
IN
= 10 MHz), the spur amplitude increases by 6 dB!
Hence, as system designers consider sampling in higher
Nyquist zones, this relationship becomes very important
to them.
Sometimes the fast Fourier transform (FFT) plot can be
a bit misleading when one is trying to trace spurs back to
their origins. If the clock spur is relatively far from the
clock frequency, the generated spurs of the ADC can get
pushed outside the plot’s boundaries—either to negative
frequencies or beyond f
CLK
/2. The spurs then alias back in-
band and generate an asymmetric FFT plot, as demon-
strated in Figure 3.
Figure 3. Spurs pushed outside the FFT band and aliased back in-band
m
m
m
m
f
S1
f
S2
f /2
CLK
f
S1
f
S2
f /2
CLK
7
Analog Applications Journal
3Q 2009
www.ti.com/aaj
High-Performance Analog Products
Data Acquisition
Texas Instruments Incorporated
Measurements
To further demonstrate the impact of the spur’s frequency
and amplitude, the following experiment was set up (see
Figure 4). A low-jitter-signal generator was used to provide
a sine-wave input signal to TI’s ADS5463 evaluation module
(EVM). The ADC input was sampled with a 122.88-MHz
clock, and a power combiner and third signal generator
were used to mix a spur into the clock’s frequency. This
way the frequency and amplitude of the spur could easily
be adjusted. The spur’s amplitude and frequency were
verified with a phase-noise analyzer.
For the first experiment, the spur generator was set up
to output a tone with a frequency of 102 MHz and an
amplitude of –30 dBm. The power combiner reduced the
clock and spur signals by about 3 dB. The phase-noise
analyzer showed the amplitudes of the clock and spur at
–9 dBm and about –33 dBm, respectively, with an offset
(m) of about 20.9 MHz (122.88 MHz – 102 MHz) as illus-
trated in the screen capture in Figure 5. As previously
derived, this setup generated two spurs with a spur-
amplitude scale factor of
Figure 4. Test setup to mix a spur and
clock signal
f
CLK
f
S
Power
Combiner
Spur
Generator
Clock Generator
122.88 MHz
Phase-Noise
Analyzer
Clock
Data
f
IN
Signal
Generator
ADS5463
f
10
21
22 88
MHz
=−
IN
CLK
BA
−+
20
log
=−
33 dBm
−−
(
9
dBm
)
+
20
log
51 8
.
dBc
2
×
f
×
.
MHz
and spur frequencies of
f
=+=
f
m
10 MHz
+
20 9
.
MHz
=
309
.
MHz and
S
1
2
IN
f
=−=
f
m Hz
10
−
20
.9
MHz
=− .
109
MHz
.
S
IN
Figure 5. Phase-noise plot of 102-MHz spur with
–33-dBm amplitude
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
33 dB
f= 102 MHz (–30 dBm),
m =20-MHz Offset
S
100
1 k
10 k 100 k
Frequency (Hz)
1 M
10 M
8
High-Performance Analog Products
www.ti.com/aaj
3Q 2009
Analog Applications Journal
Texas Instruments Incorporated
Data Acquisition
The resulting FFT plot of the ADS5463
output is shown in Figure 6. The gener-
ated spurs are about 52 dB lower than
the input signal and are located at 10.9
and 30.9 MHz. This matches the calcu-
lated values very closely.
Next, the spur amplitude was lowered
from –30 dBm to –40 dBm. It was expect-
ed that the S1 and S2 spur amplitudes
would drop by 10 dB as well. This was
confirmed with the FFT plot of the
ADS5463 output, as illustrated in
Figure 7. The frequencies of the spurs
stayed the same.
As discussed previously, the spur
amplitude is highly dependent upon the
frequency of the input signal. To further
illustrate this, the frequency of the input
signal was increased from 10 MHz to
100 MHz. This changed the spur-
amplitude scale factor to
Figure 6. FFT output of 102-MHz, –30-dBm clock spur
0
f= 10-MHz sine wave
f= 102 MHz (–30 dBm)
IN
S
–20
52 dB
f=
S1
30.9 MHz
f= 10.9 MHz
S2
–40
–60
–80
–100
–120
0
10
20
30
40
50
60
Frequency
(
MHz
)
f
100 MHz
=− −=−
IN
=−
BA20log
−+
33 dBm(9 dBm)
−−
+
20log
24
7.8
31.8 dBc
2
×
f
2
×
122.88 MHz
CLK
and the frequencies of the two spurs to
f
=− +=−
f
f
102 MHz
+
100
MHz
=−
2
MHz and
S
1
S
IN
f
=− −=−
f
f
102
MH
z
−
100
Hz
=−
202
MHz
.
S
2
S
IN
Aliasing them back in-band generated two spurs,
f
=−
2
MHz
=+
2
MHz and
S
S
1
2
f
=−
202
MHz
+×
(
2
122 88
.
MHz
)
=
43 8
.
MHz
.
Figure 7. FFT output of 102-MHz, –40-dBm clock spur
0
f= 10-MHz sine wave
f= 102 MHz (–40 dBm)
IN
S
–20
62 dB
f= 10.9 MHz
S2
f=
S1
30.9 MHz
–40
–60
–80
–100
–120
0
10
20
30
40
50
60
Frequency
(
MHz
)
9
Analog Applications Journal
3Q 2009
www.ti.com/aaj
High-Performance Analog Products
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