mega323.pdf

Features

• High-performance, Low-power AVR ® 8-bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution

– 32x8GeneralPurposeWorkingRegisters

– Fully Static Operation

– Up to 8 MIPS Throughput at 8 MHz

– On-chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 32K Bytes of In-System Self-programmable Flash

Endurance: 1,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

–1KByteEEPROM

Endurance: 100,000 Write/Erase Cycles

– 2K Bytes Internal SRAM

– Programming Lock for Software Security

• JTAG (IEEE Std. 1149.1 Compliant) Interface

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

– Boundary-Scan Capabilities According to the JTAG Standard

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP and 44-lead TQFP

• Operating Voltages

– 2.7 - 5.5V (ATmega323L)

– 4.0 - 5.5V (ATmega323)

• Speed Grades

– 0 - 4 MHz (ATmega323L)

– 0 - 8 MHz (ATmega323)

8-bit

Microcontroller

with 32K Bytes

of In-System

Programmable

Flash

ATmega323

ATmega323L

Preliminary

Not Recommend for

New Designs. Use

ATmega32.

Rev. 1457F–AVR–09/02

Pin Configurations

PDIP

(XCK/T0) PB0

(T1) PB1

(INT2/AIN0) PB2

(OC0/AIN1) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP) PD6

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

AGND

AVCC

PC7 (TOSC2)

PC6 (TOSC1)

PC5 (TDI)

PC4 (TDO)

PC3 (TMS)

PC2 (TCK)

PC1 (SDA)

PC0 (SCL)

PD7 (OC2)

TQFP

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(RXD) PD0

(TXD) PD1

(INT0) PD2

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

AGND

AVCC

PC7 (TOSC2)

PC6 (TOSC1)

PC5 (TDI)

PC4 (TDO)

ATmega323(L)

1457F–AVR–09/02

ATmega323(L)

Overview

TheATmega323isalow-power CMOS 8-bit microcontroller basedonthe AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

theATmega323achieves throughputs approaching 1 MIPS per MHz allowing the sys-

temdesigner to optimize power consumption versus processing speed.

Block Diagram

Figure 1. Block Diagram

PA0-PA7

PC0 - PC7

VCC

PORTA DRIVERS

PORTC DRIVERS

GND

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

AVCC

ANALOG MUX

ADC

JTAG

INTERFACE

AGND

AREF

2-WIRE SERIAL

INTERFACE

OSCILLATOR

XTAL1

INTERNAL

REFERENCE

INTERNAL

OSCILLATOR

XTAL2

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

RESET

PROGRAM

FLASH

SRAM

MCU CONTROL

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTERS

INTERRUPT

UNIT

INSTRUCTION

DECODER

CONTROL

LINES

ALU

EEPROM

STATUS

INTERNAL

CALIBRATED

OSCILLATOR

PROGRAMMING

LOGIC

SPI

USART

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD7

1457F–AVR–09/02

TheAVRcore combines a rich instruction setwith32 general purpose working registers.

All the 32 registers are directly connectedtotheArithmetic Logic Unit (ALU), allowing

two independent registers to be accessedinone single instruction executedinone clock

cycle. The resulting architecture is more codeefficient while achieving throughputs up to

tentimesfaster than conventional CISC microcontrollers.

TheATmega323providesthe following features: 32Kbytes of In-System Programmable

Flash, 1Kbytes EEPROM, 2KbytesSRAM, 32 general purpose I/Olines, 32 general

purpose working registers, a JTAGinterface for Boundary-Scan, On-chip Debugging

support and programming, three flexible Timer/Counters with compare modes, internal

and external interrupts, a serial programmable USART, a byte orientedTwo-wire Serial

Interface, an 8-channel, 10-bit ADC, a programmable Watchdog Timerwithinternal

Oscillator, an SPI serial port, and six software selectable powersaving modes. The Idle

mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt

system to continue functioning. The Power-down mode savesthe register contents but

freezesthe Oscillator, disabling all other chip functions until the next interrupt or Hard-

wareReset. In Power-save mode,the asynchronous timer continues to run, allowing the

usertomaintainatimerbase while the rest of the device is sleeping. TheADC Noise

Reduction mode stops the CPU and all I/O modules except asynchronous timer and

ADC, to minimize switching noise during ADC conversions. In Standby mode,the crys-

tal/resonator Oscillator is running while the rest of the device is sleeping. This allows

very fast start-up combinedwithlow-powerconsumption. In Extended Standby mode,

both the main Oscillator and the asynchronous timer continue to run.

The device is manufacturedusingAtmel’s high-density non-volatile memory technology.

The On-chip ISP Flash allows the Program memory to be re-programmedIn-System

throughanSPIserial interface,byaconventional non-volatile memory programmer, or

by an On-chip Boot Program running on theAVRcore. The Boot Program can use any

interface to download the application program in theApplication Flash memory. By com-

bining an 8-bit RISC CPU with In-System ProgrammableFlash on a monolithic chip, the

Atmel ATmega323 is a powerful microcontroller that provides a highly flexible and cost

effective solution to many embedded control applications.

TheATmega323 AVR is supportedwithafullsuite of program and systemdevelopment

tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators, and evaluation kits.

Pin Descriptions

VCC

Digital supply voltage.

GND

Digital ground.

Port A (PA7..PA0)

Port A servesasthe analog inputs to theA/DConverter.

Port A also servesasan8-bitbi-directional I/O port, if theA/DConverter is not used.

Port pins can provide internal pull-up resistors (selectedforeach bit). The Port A output

buffers can sink 20 mA and can drive LED displays directly. WhenpinsPA0 to PA7 are

used as inputs and areexternally pulledlow,they will source current if the internal pull-

up resistors are activated. The Port A pins are tri-statedwhenareset condition

becomesactive, evenifthe clock is not running.

ATmega323(L)

1457F–AVR–09/02

ATmega323(L)

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/Oportwithinternal pull-up resistors (selectedforeach

bit). The Port B output buffers can sink 20 mA. As inputs, Port B pins that areexternally

pulled low will source current if the pull-up resistors are activated. The Port B pins are

tri-statedwhenareset condition becomesactive, evenifthe clock is not running.

Port B also servesthe functions of various special featuresoftheATmega323 as listed

on page139.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selectedforeach

bit). The Port C output buffers can sink 20 mA. As inputs, Port C pins that areexternally

pulled low will source current if the pull-up resistors are activated. The Port C pins are

tri-statedwhenareset condition becomesactive, evenifthe clock is not running.

Port C also servesthe functions of the JTAGinterface and otherspecial featuresofthe

ATmega323aslisted on page146. If the JTAGinterface is enabled, the pull-up resistors

on pins PC5 (TDI), PC3 (TMS) and PC2 (TCK) will be activated evenifaResetoccurs.

Port D (PD7..PD0)

Port D is an 8-bit bidirectional I/Oportwithinternal pull-up resistors (selectedforeach

bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that areexternally

pulled low will source current if the pull-up resistors are activated. The Port D pins are

tri-statedwhenareset condition becomesactive, evenifthe clock is not running.

Port D also servesthe functions of various special featuresoftheATmega323 as listed

on page 151.

RESET

Reset input.Alow levelonthispinformore than 500 ns will generate a Reset, evenif

the clock is not running. Shorter pulsesare not guaranteedtogenerate a Reset.

XTA L 1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTA L 2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port A and theA/DConverter. It should beexternally

connectedtoV CC , eveniftheADC is not used. If theADC is used, it should be con-

nectedtoV CC through a low-pass filter. See page 127 for details on operation of the

ADC.

AREF

AREF is the analog reference pin for theA/DConverter.For ADC operations, a voltage

in the range2.56V to AVCC can be appliedtothispin.

AGND

Analog ground. If the board has a separate analog ground plane, this pin should be con-

nected to this ground plane. Otherwise,connect to GND.

1457F–AVR–09/02

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