First-Time-Right_Design_of_RF-Microwave_Amplifiers_-_copyright.pdf

First-Time-Right Design Of RF/Microwave Class A Power Amplifiers Using

Only S-Parameters

The sequel to "Tandem RF software programs streamline the design of power amplifiers" [7]

By Ivan Boshnakov ( ivanb@aerial.co.uk ), Senior Principal Engineer

Aerial Facilities Limited ( www.aerialfacilities.com )

This article describes and discusses a procedure of how to design RF/Microwave Class A

power amplifiers in a very efficient and highly accurate manner when the only initial data available are

the S-parameters of the transistors. As in the prequel [7], two software programs are used in

conjunction and interaction: a specialized RF/Microwave amplifier design software tool and a general-

purpose simulator (nodal analysis program). This time the simulator is not used for its nonlinear

analysis capabilities but mostly for its integrated layout EM simulation capabilities.

The Power Parameters Design Method

S - parameters can be used to design Class A amplifiers for optimum gain and input/output

return loss at the biasing point at which the transistor S - parameters have been measured. If Noise

Parameters are available and they are combined with the S-parameters, it also becomes possible to

design for optimum Noise Figure (NF) and the associated available power gain (G anopt ). The S-

parameters by themselves do not allow for controlling the output power obtained from each stage of

the amplifier to be designed . The power of interest in a Class A amplifier is usually the maximum

linear output power which is universally accepted to be the power at the 1dB compression point of the

gain, that is, P1dB. As with the Noise Parameters, which are needed to control the noise performance

of an amplifier, some kinds of Power Parameters are needed to design for P1dB.

One method of designing and analyzing for P1dB is to use non-linear transistor models and

non-linear (harmonic-balanced) simulators. The biggest problem here is that non-linear models are

often not readily available. The manufactures of transistors rarely provide them, and the equipment and

software that can be used to extract the non-linear models are very expensive and few companies can

afford them. The same applies to the method of using tuners to extract the optimum input and output

impedances, or the load-pull constant power contours of the transistors. Of course these methods are

unavoidable when very heavy non-linear modes of operation are used and information for the signal

distortion is needed.

Cripps, in his usual manner of defying the “conventional wisdom”, introduced and developed

in [2], [3] and [4] a simple approach for estimating and designing for the maximum output power of

mildly non-linear (Class A) power stages. In this approach the transistor is approximated by a very

simple equivalent model consisting of the intrinsic voltage controlled current source (generator) and the

parasitic output parallel capacitor and series inductor. The weakly non-linear effects are ignored and

the transconductance is considered to be linear until the voltage across it and/or the current supplied by

it clips strongly when voltage pinchoff and/or current saturation is reached. Under these assumptions,

Cripps developed linear mathematical expressions, which tie together the load-line and the voltage and

current limits across the intrinsic generator with the external load and the output power delivered to this

load. He showed how to present the relation between the intrinsic load-line and the external impedance

on a Smith Chart as constant output power (load-pull) contours.

The Cripps Approach became very popular because of its simplicity and the satisfactory

results it provides in many cases. The simple three-element equivalent model can easily be extracted

when a full linear equivalent circuit is fitted to the S - parameters of the particular transistor. This

approach is, however, often not general enough. Some of its limitations are that it does not allow for

feedback or transistor losses. In [3] Cripps pointed out that it is a simple task to implement the

equations presented in the article into a linear simulator to simulate the power performance in the same

manner that most simulators compute noise figure. He also pointed out that, with a slightly more

innovative approach, the effect of the feedback could also be taken in account.

The Cripps Approach can be considered to be the basis for the Power Parameters introduced

by Abrie in [1] and described more thoroughly in [5]. Abrie used mathematical mapping functions to

relate “the intrinsic voltages to the external voltages and the intrinsic output current”. This innovation

takes away (lifts) in a very elegant manner all the limitations of the Cripps Approach. The Power

Parameters take in account feedback and losses, as well as changes in the transistor configuration. This

makes their application universal and allows for most versatile amplifier design. The Power

Parameters allow P1dB of each stage in multistage amplifier designs to be controlled and analyzed in

relation to the other stages. Interestingly enough the Power Parameters behaviour resembles the Noise

Parameters behaviour. P1dB is independent of the source impedance, while NF is independent of the

load impedance. Feedback (series or parallel) affects P1dB in a similar manner as NF. Power

Parameters , however, have one distinctive advantage on the Noise Parameters : They do not require

measurement with special and expensive equipment and tedious setup and measurement procedures.

The only information required is the linear model of the transistor, the bias point , the I/V curves

boundaries and the slopes of these boundaries (if available). If a small-signal model is not available, the

required model can usually be extracted easily from the S-parameters.

The Software Tools

Power Parameters can be implemented or added into any linear simulator, but for the time

being they are available only in MultiMatch Amplifier Design Wizard. MultiMatch is specifically

dedicated to the design of amplifiers and oscillators. It combines linear frequency domain simulation

and iterative synthesis of passive networks. Two kinds of passive networks can be synthesized. The

first type is modification networks as they are defined in MultiMatch. The modification networks

usually contain resistors and they could be either loading the transistor or they could be feedback

sections (series or parallel). Loading and feedback can of course also be simultaneously implemented.

The other kind of synthesis is for purely reactive, lossless matching networks. The control parameters

for the synthesis of the passive networks are the requirements for gain, return loss, stability, noise

figure, P1dB, oscillator start-up frequency and tuning range, etc. The design procedures are actually set

up to synthesize amplifiers or oscillators, not just passive networks.

MultiMatch allows linear power amplifiers to be designed very efficiently, but in order for the

design to produce first-time-right results, additional special care must be taken of the discontinuities of

the matching networks designed for high power RF transistors, as is emphasized in [6]. That can be

done by using MultiMatch in conjunction with a nodal analysis simulator, which incorporates layout

EM simulation. As in [7], Microwave Office was chosen for the designing the amplifier considered here.

Some of the reasons for choosing Microwave Office are that before everything it is very user-friendly

and, with its Application Programming Interface, it provides the possibility for seamless interaction

with other software tools. In this case MultiMatch exports its schematics into script files that can be

executed inside Microwave Office to translate the MultiMatch schematics into Microwave Office

schematics.

The Design Problem

It was necessary to develop a 5W Class A single-ended amplifier stage for the 2.1-2.2 GHz

frequency band with gain of 10-11dB. The single-ended stage was subsequently used to configure a

balanced 10W amplifier stage. The transistor chosen was the Mitsubishi MGF909A which delivers a

minimum of 37dBm of P1dB at the biasing point of 10V, 1.3A. Mitsubishi provides S-parameters for

this bias point but does not offer any nonlinear model or load-pull data for the transistor.

The Design Procedure

The design started in MultiMatch. A design bandwidth of 2.075-2.225 GHz with a step of

25MHz was set up; substrate parameters were entered, etc. Then a command for modifying a transistor

was invoked (Figure 1).

Figure 1. Transistor modification starting window

The first thing to be done when designing for P1dB is to fit a linear model to the S-parameters

the transistor . Figure 2 shows the window dedicated to this purpose. The measured S-parameters and

the parameters associated with the model fitted are compared in Figure 3. Note the optimization facility

in Figure 2 and the option to display the graph mentioned. The bias point (dc operating point) and the

I/V Curve Boundaries are also specified at this point. With a model fitted and the load-line boundaries

specified, MultiMatch can calculate the Power Parameters and predict and synthesize for P1dB.

Figure 2. Transistor model fitting facility

Figure 3. Graph showing the result of the fitting

The next step was to do a general analysis of the transistor capabilities. This showed that the

maximum P1dB that can be achieved is close to 38dBm and that the gain could be up to 13dB when the

output is matched for maximum P1dB. The k-factor (Rollette stability factor) of the transistor shows

that the transistor is unconditionally stable above 1.8GHz and becomes less and less stable towards

lower frequencies. At this stage of the design, it is possible to guide MultiMatch to synthesize

modification networks at the input that would contain resistors and that would stabilize the transistor,

level the gain and pre-match the transistor. The modification networks can, however, be a bit tricky to

realize physically with surface-mount components at the input of the transistor when the transistor has

very low input impedance. It was decided to get out of the modification section, proceed to synthesis of

output and input matching networks and then add at the very input a network to provide the required

stability at the low frequencies.

The next action was to execute the command that starts the synthesis of output networks for

the particular transistor stage. The MultiMatch Amplifier Design Wizard goes through a sequence of

specification (setting-up) windows in an interactive dialogue with the designer. The dialog boxes for

specifying the target load-pull P1dB contours are shown in Figures 4 and 5. Then follow dialogue

boxes with tables (not shown here) from which the impedances to be used to extract the required P1dB

can be selected (The power remains the same around any target contour, but the other parameters of

interest will vary).

Figure 4. Load-pull contours set-up window Figure 5. Load-pull contours

In this case MultiMatch was instructed to select the impedances for the maximum P1dB. With

the target load terminations defined, MultiMatch switched to the Synthesis Section Menus and the

syntheses of the output matching network was initiated. The synthesis of the matching networks is

done again in an interactive mode between the program and the designer (It could take quite a few trials

before a satisfactory solution is found). At this stage of the design process the designer should also start

worrying about the effect of the discontinuities in the microstrip network that would be synthesized.

The first few synthesis trials were done just to get an estimate of the most problematic discontinuities

and how to approach solving the problems that they would create. It became obvious that the biggest

discontinuity would be the step between the output pin of the transistor (0.6mm) and the first low-

impedance transformation line (13.4 , 10 mm width). It was decided to first simulate this step in the

EM layout simulator of Microwave Office. Figure 6 shows the EM simulation of the step and the

current distribution in it. The current distribution reveals where the discontinuity is actually taking

place and this was taken in account when the two reference planes were placed for the extraction of the

S-parameters of the step (see Figure 7).

Figure 6. EM step with current distribution Figure 7. Reference planes of the step

The S-parameters of the step were imported into MultiMatch (Figure 8) and the synthesis of

the output network for maximum P1dB was started again. The synthesized solution is given in Figure 9

in schematic form and in layout form in Figure 10.

Figure 8. EM simulated step added to the input and output of the transistor

Figure 9. The synthesized output network added at the output of the transistor

Figure 10. The layout of the output matching network

The high impedance parallel stub terminated with a capacitor to ground was not part of the synthesized

solution. It was added manually for biasing purposes and it’s about 90° long at the middle of the

frequency band.

The synthesis of the input matching network for maximum gain was performed in a very

similar manner. A stabilizing network consisting of a resistor and shorted (by capacitor) stub was added

at the very input as was mentioned above and serves as a biasing network too. The layout for the full

amplifier stage generated by MultiMatch is presented in Figure 11.

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