STD2NB50.pdf

(453 KB) Pobierz
STD2NB50
STD2NB50-1
N-CHANNEL 500V - 5
- 1A DPAK / IPAK
PowerMesh™ MOSFET
W
TYPE
V DSS
R DS(on)
I D
STD2NB50
STD2NB50-1
500V
500V
< 6
W
< 6
1 A
1 A
W
TYPICAL R DS (on) = 5
W
n
3
3
100% AVALANCHE TESTED
2
n
1
1
VERY LOW INTRINSIC CAPACITANCES
n
ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
n
DPAK
IPAK
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an ad-
vanced family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company’s proprieraty edge termi-
nation structure, gives the lowest RDS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteris-
tics.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
n
SWITH MODE POWER SUPPLIES (SMPS)
LIGHTING FOR INDUSTRIAL AND CONSUMER
ENVIRONMENT
n
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V DS
Drain-source Voltage (V GS = 0)
500
V
V DGR
Drain-gate Voltage (R GS = 20 k
W
)
500
V
V GS
Gate- source Voltage
± 30
V
I D
Drain Current (continuos) at T C = 25°C
1
A
I D
Drain Current (continuos) at T C = 100°C
0.63
A
I DM ( l )
Drain Current (pulsed)
4
A
P TOT
Total Dissipation at T C = 25°C
40
W
Derating Factor
0.32
W/°C
dv/dt(1)
Peak Diode Recovery voltage slope
3.5
V/ns
T stg
Storage Temperature
–65 to 150
°C
T j
Max. Operating Junction Temperature
150
°C
(•)Pulse width limited by safe operating area
(1)I SD
1A, di/dt
200A/µs, V DD
V (BR)DSS , T j
T JMAX.
September 2001
£
£
£
£
1/10
786547399.090.png 786547399.101.png 786547399.111.png 786547399.122.png 786547399.001.png 786547399.012.png 786547399.022.png 786547399.033.png 786547399.044.png 786547399.046.png 786547399.047.png 786547399.048.png 786547399.049.png 786547399.050.png 786547399.051.png 786547399.052.png 786547399.053.png 786547399.054.png 786547399.055.png 786547399.056.png 786547399.057.png 786547399.058.png 786547399.059.png 786547399.060.png 786547399.061.png 786547399.062.png 786547399.063.png 786547399.064.png 786547399.065.png 786547399.066.png 786547399.067.png 786547399.068.png 786547399.069.png 786547399.070.png 786547399.071.png 786547399.072.png
 
STD2NB50/STD2NB50-1
THERMAL DATA
Rthj-case
Thermal Resistance Junction-case Max
3.125
°C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
100
°C/W
T l
Maximum Lead Temperature For Soldering Purpose
275
°C
AVALANCHE CHARACTERISTICS
Symbol
Parameter
Max Value
Unit
I AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T j max)
1
A
E AS
Single Pulse Avalanche Energy
(starting T j = 25 °C, I D = I AR , V DD = 50 V)
40
mJ
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V (BR)DSS
Drain-source
Breakdown Voltage
I D = 250 µA, V GS = 0
500
V
I DSS
Zero Gate Voltage
Drain Current (V GS = 0)
V DS = Max Rating
1
µA
V DS = Max Rating, T C = 125 °C
50
µA
I GSS
Gate-body Leakage
Current (V DS = 0)
V GS = ±30V
±100
nA
ON (1)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V GS(th)
V DS = V GS , I D = 250µA
Gate Threshold Voltage
2.3
3
3.7
V
R DS(on)
Static Drain-source On
Resistance
V GS = 10V, I D = 0.5 A
5
6
W
DYNAMIC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g fs (1)
Forward Transconductance
V DS > I D(on) x R DS(on)max,
I D = 0.5 A
0.75
S
C iss
V DS = 25V, f = 1 MHz, V GS = 0
Input Capacitance
185
pF
C oss
Output Capacitance
35
pF
Reverse Transfer
Capacitance
C rss
4
pF
2/10
786547399.073.png 786547399.074.png 786547399.075.png 786547399.076.png 786547399.077.png 786547399.078.png 786547399.079.png 786547399.080.png 786547399.081.png 786547399.082.png 786547399.083.png 786547399.084.png 786547399.085.png 786547399.086.png 786547399.087.png 786547399.088.png 786547399.089.png 786547399.091.png 786547399.092.png 786547399.093.png 786547399.094.png 786547399.095.png 786547399.096.png 786547399.097.png 786547399.098.png 786547399.099.png 786547399.100.png 786547399.102.png 786547399.103.png 786547399.104.png 786547399.105.png
 
STD2NB50/STD2NB50-1
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t d(on)
Turn-on Delay Time
V DD = 200V, I D = 0.5A
R G = 4.7
20
ns
V GS = 10V
(see test circuit, Figure 3)
W
t r
Rise Time
24
ns
Q g
Total Gate Charge
V DD = 4000V, I D = 1A,
V GS = 10V
7
10
nC
Q gs
Gate-Source Charge
2.5
nC
Q gd
Gate-Drain Charge
3.5
nC
SWITCHING OFF
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t r(Voff)
V DD = 400V, I D = 1 A,
R G = 4.7
Off-voltage Rise Time
20
ns
V GS = 10V
(see test circuit, Figure 5)
W,
t f
Fall Time
24
ns
t c
Cross-over Time
30
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I SD
Source-drain Current
1
A
I SDM (2)
Source-drain Current (pulsed)
4
A
V SD (1)
I SD = 1A, V GS = 0
Forward On Voltage
1.5
V
t rr
I SD = 1A, di/dt = 100A/µs,
V DD = 100V, T j = 150°C
(see test circuit, Figure 5)
Reverse Recovery Time
330
ns
Q rr
Reverse Recovery Charge
780
µC
I RRM
Reverse Recovery Current
4.7
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedence
3/10
786547399.106.png 786547399.107.png 786547399.108.png 786547399.109.png 786547399.110.png 786547399.112.png 786547399.113.png 786547399.114.png 786547399.115.png 786547399.116.png 786547399.117.png 786547399.118.png 786547399.119.png 786547399.120.png 786547399.121.png 786547399.123.png 786547399.124.png 786547399.125.png 786547399.126.png 786547399.127.png 786547399.128.png 786547399.129.png 786547399.130.png 786547399.131.png 786547399.132.png 786547399.002.png 786547399.003.png 786547399.004.png 786547399.005.png 786547399.006.png 786547399.007.png 786547399.008.png 786547399.009.png 786547399.010.png 786547399.011.png 786547399.013.png 786547399.014.png 786547399.015.png
 
STD2NB50/STD2NB50-1
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/10
786547399.016.png 786547399.017.png 786547399.018.png 786547399.019.png 786547399.020.png 786547399.021.png 786547399.023.png 786547399.024.png 786547399.025.png 786547399.026.png 786547399.027.png 786547399.028.png 786547399.029.png 786547399.030.png 786547399.031.png 786547399.032.png 786547399.034.png 786547399.035.png 786547399.036.png 786547399.037.png 786547399.038.png
STD2NB50/STD2NB50-1
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/10
786547399.039.png 786547399.040.png 786547399.041.png 786547399.042.png 786547399.043.png 786547399.045.png
 
Zgłoś jeśli naruszono regulamin