AN335.pdf

Digital PLL Synthesis

National Semiconductor

Application Note 335

Craig Davis

Tom Mills

Keith Mueller

April 1983

I. System Concepts

INTRODUCTION

Digital tuning systems are fast replacing the conventional

mechanical systems in AM/FM and television receivers.

The desirability of the digital approach is mainly due to the

following features:

Y Precise tuning of station frequencies

Y Exact digital frequency display

Y Keyboard entry of desired frequency

Y Virtually unlimited station memory

Y Up/down scanning through the band

Y Station ``search'' (stop on next active station)

Y Power on to the last station

Y Easy option for time-of-day clock

In addition, recent developments in large scale integrated

circuit technology and new varactor diodes for the AM band

have made the cost-benefit picture for digital tuning very

attractive. System partitioning is extremely important in opti-

mizing this cost-benefit picture, as will be discussed.

SYSTEM DESCRIPTION

A simplified block diagram of a typical digitally tuned receiv-

er is shown inFigure1. Notice this receiver could be one for

AM, FM, marine radio, or television; it makes no difference.

The frequency synthesizer block generates the local oscilla-

tor frequency for the receiver, just as a conventional me-

chanical tuner would. However, the phase-locked-loop

(PLL) acts as an integral frequency multiplier of an accurate

crystal controlled reference frequency while the mechanical

type provides a continuously variable frequency output with

no reference. Some method of controlling the value of the

multiplier for channel tuning must be provided. The other

RF, IF, and audio/video circuitry will be the same as in the

mechanical tuning method.

There are many different ways to partition the frequency

synthesizer system to perform the digital tuning function.

TL/F/5269±1

FIGURE 1. Block Diagram of a Digitally Tuned Receiver

COPS TM is a trademark of National Semiconductor Corp.

C 1995 National Semiconductor Corporation

TL/F/5269

RRD-B30M105/Printed in U. S. A.

PROGRAMMABLE CONTROLLER FUNCTION

The most cost-effective application of different IC process

technologies is shown inFigure2. The controller is separate

from the PLL. The controller can be as simple as a mask

programmable microcontroller* or as complicated as a high-

powered microprocessor system. It can be done most eco-

nomically with NMOS technology because of the logic den-

sity possible and the small size of the RAM/ROM memory

cells. It could also be CMOS for extremely low power con-

sumption in standby mode.

BASIC PHASE-LOCKED-LOOP FUNCTION

The DS8906/7/8 series of PLLs utilize a dual-modulus fre-

quency synthesis technique. The reasons for this and the

PLL itself will now be discussed.

Figure3 is a diagram of the most simple phase-locked-loop.

A particular reference frequency is generated by a crystal

oscillator and some fixed divider, and this goes into one side

*Such as National's COP TM family.

of a digital phase comparator. A voltage controlled oscillator

(VCO) feeds directly into the other input of the phase com-

parator. The output of the phase comparator is an error sig-

nal which is filtered and fed back to the VCO as a DC con-

trol voltage.

In lock, the phase error must be zero, so f IN equals f REF .

This system provides only one output frequency, that being

equal to the reference frequency.

Figure4 is basically the same but now a programmable di-

vide-by-N counter is between the VCO and the phase com-

parator. The input to the phase comparator (f IN ) now be-

comes the output frequency of the VCO (f OUT ) divided by N,

where N is the division code loaded into the programmable

counter. This means f OUT /N must equal f REF . Thus, the

VCO output frequency becomes N c f REF , and f OUT can

now be changed in integral steps of f REF by merely chang-

ing N.

TL/F/5269±2

FIGURE 2. System Block Diagram

f IN e f REF

TL/F/5269±3

FIGURE 3. Basic Phase-Locked-Loop

f IN e f REF

f IN e

f OUT

N e f REF

f OUT e N c t REF x f STEP

e f REF

TL/F/5269±4

FIGURE 4. Basic PLL Frequency Synthesizer

f OUT

In applications where the output frequency desired exceeds

the maximum clock frequency of available programmable

dividers, a common solution is to add a prescaler preceding

the programmable divider, as shown inFigure5. In this case

f OUT e N(M c f REF ) and so the output frequency step size

becomes M c f REF . So, while this technique allows higher

frequency operation, it does so at the expense of either

increased channel spacing for a given reference frequency,

or decreased reference frequency if a specific channel

spacing is required. This latter limitation is often undesirable

as it can cause increased lock-on time, decreased scanning

rates, and sidebands at undesirable frequencies.

Figure 6 shows the basic dual-modulus scheme. Here, a

dual-modulus prescaler is substituted for the fixed prescaler

and the modulus is controlled by programmable counters.

The advantage to this approach is that the step size is again

equal to the reference frequency while the prescaling still

allows the programmable counters to operate at lower fre-

quencies. As in the fixed prescale technique, only the pre-

scaler needs to be high speed. The DS8906/7/8 prescale

by 7/8 for AM and in a similar fashion by 63/64 in FM.

f IN e f REF

f IN e

f OUT

N c M

FIGURE 5. PLL Frequency Synthesizer with Fixed Prescaler

f OUT

N c M e f REF

f OUT e (N c M) f REF

TL/F/5269±5 f OUT e N(M c f REF )

x f STEP e M c f REF

f OUT

N e f REF

f OUT e N c f REF x f STEP e f REF

*if f REF e f IN , then ``tuned''

if f REF i f IN , then ``not tuned''

f IN e

TL/F/5269±6

FIGURE 6. Basic Dual-Modulus Frequency Synthesizer

II. Application Hints

VOLTAGE CONTROLLED OSCILLATORS

In all radio and television applications, the voltage con-

trolled oscillator (VCO) is a varactor tuned, LC type of cir-

cuit. The LC circuit is used over the various RC current con-

trolled circuits because of their superior noise characteris-

tics. Figure7 shows a collection of popular VCOs used in

radio and television tuners. The AM VCO is a Hartley design

chosen for wide tuning range. Commonly used varactors will

show a capacitance change of 350 pF at 1V to 20 pF at 8V,

which if used in a low capacitance oscillator circuit, can pro-

duce a tuning range approaching 3 to 1.

In the higher frequency ranges, above 50 MHz, Colpitts os-

cillators are used because stray circuit capacitance will be in

parallel with desired feedback capacitance and not cause

undesirable spurious resonances that might occur with the

tapped coil Hartley design. The FM VCO shown is a ground-

ed base design with feedback from collector to emitter. A

UHF television oscillator is also shown. It too is a grounded

base oscillator, but using a transmission line as the reso-

nant element instead of a coil. The transmission line and

tuning capacitors are arranged in q network which offers

improved noise characteristics over a parallel tuned circuit.

This circuit will tune over almost an octave.

Hartley Oscillator

TL/F/5269±7

50 kHz E 15 MHz VCO

Tuning range j 3:1

Colpitts Oscillator

TL/F/5269±8

50 MHz E 300 MHz VCO

Tuning range j 2:1

TL/F/5269±9

500 MHz E 1000 MHz VCO

Tuning range j 1.8:1

FIGURE 7. Typical VCO Circuits (Typical Values Shown)

PLL LOOP FILTER CALCULATIONS

Andrzej Przedpelski, in two articles published in Electronic

Design ( Ý 19, Sept. 13, 1978 and Ý 10, May 10, 1978) ex-

plains how to calculate the three time constants associated

with a third order type 2 loop which is typically used with the

DS8906/7/8 series. Figure 8 explains his method and

shows a sample calculation. His articles illustrate how to

calculate three time constants, and plot open loop gain and

phase, and closed loop noise response.

It should be noted that VCO gain, K V , is in terms of radians

per second per volt, and phase detector gain, K D , is in terms

of amps per radian. The phase detector gain for the

DS8906/7/8 series is g I OUT divided by 4 q .

Figure 9 illustrates an example calculation of time con-

stants, and a plot of open loop gain and phase based on the

preceding analysis.

REFERENCES

1. Manassewitsch V., ``Frequency Synthesizers'' (Wiley,

New York, 1976)

2. Rohde, A. L., ``Digital PLL Frequency Synthesizers''

(Prentice Hall, Englewood Cliffs, 1983)

3. Egan, W. F., ``FrequencySynthesisByPhaseLock'' (Wi-

ley, New York, 1981)

T1 e R1C1

T1 e R1C2

I O

1 a ST1

SC1 (1 a ST2)

G(S) e

K D K V

NS 2 C1

1 a ST1

1 a ST2

T2 e

1 b tan w cos w

0 O cos w

T1 e

0 O 2 T2

where i e desired phase margin

0 O e loop natural frequency

& closed loop bandwidth

Note: DS8909 op amp required C3 & 1000 pF for compensation.

FIGURE 8. Third Order Type 2 Loop

C1 e

K D K V

N 0 O 2

b 0 O T1 b 1

0 O T2 a 1

TL/F/5269±10

VHF loop, running at 100 MHz, ref e 10 kHz

K V e 2.5 MHz/V e 15.7 Mrad/sec/V

K D e

400 m A

4 q

e 31.8 m A/radian

100 MHz

10 kHz e 10,000, 0 O e 2 q c 100 Hz

i e 45 § (desired phase margin)

T2 e 6.6 c 10 b 4 sec

T1 e 3.84 c 10 b 3 sec

C1 e 0.3 m F

so R1 e T1/C1 e 13 k X

C2 e T2/R1 e 0.05 m F

TL/F/5269±11

FIGURE 9. Example of Gain and Phase Calculation

N e

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