GAL16V8.PDF

FINAL

COM’L: H-5/7/10/15/25, Q-10/15/25

IND: H-10/15/25, Q-20/25

PALCE16V8 Family

EE CMOS 20-Pin Universal Programmable Array Logic

Advanced

Micro

Devices

DISTINCTIVE CHARACTERISTICS

Pin and function compatible with all 20-pin

GAL devices

Programmable output polarity

Programmable enable/disable control

Electrically erasable CMOS technology

provides reconfigurable logic and full

testability

Preloadable output registers for testability

Automatic register reset on power up

Cost-effective 20-pin plastic DIP, PLCC, and

SOIC packages

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Extensive third-party software and programmer

support through FusionPLD partners

Direct plug-in replacement for the PAL16R8

series and most of the PAL10H8 series

Fully tested for 100% programming and

functional yields and high reliability

Outputs programmable as registered or

combinatorial in any combination

5 ns version utilizes a split leadframe for

improved performance

Peripheral Component Interconnect (PCI)

compliant

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with

low-power, high-speed, electrically-erasable CMOS

technology. It is functionally compatible with all 20-pin

GAL devices. The macrocells provide a universal device

architecture. The PALCE16V8 will directly replace the

PAL16R8 and PAL10H8 series devices, with the excep-

tion of the PAL16C1.

The fixed OR array allows up to eight data product terms

per output for logic functions. The sum of these products

feeds the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial with an active-

high or active-low output. The output configuration is

determined by two global bits and one local bit

controlling four multiplexers in each macrocell.

The PALCE16V8 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced to

sum-of-products form, taking advantage of the very

wide input gates available in PAL devices. The equa-

tions are programmed into the device through floating-

gate cells in the AND logic array that can be erased

electrically.

AMD’s FusionPLD program allows PALCE16V8 de-

signs to be implemented using a wide variety of popular

industry-standard design tools. By working closely with

the FusionPLD partners, AMD certifies that the tools

provide accurate, quality support. By ensuring that third-

party tools are available, costs are lowered because a

designer does not have to buy a complete set of new

tools for each device. The FusionPLD program also

greatly reduces design time since a designer can use a

tool that is already installed and familiar.

2-36

Publication# 16493 Rev. D Amendment /0

Issue Date: February 1996

AMD

BLOCK DIAGRAM

I 1 – I 8

C LK / I 0

Programmable AND Array

32 x 64

MACRO

MC 0

MC 1

MC 2

MC 3

MC 4

MC 5

MC 6

MC 7

OE/I 9

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

16493D-1

CONNECTION DIAGRAMS

Top View

DIP/SOIC

PLCC/LCC

CLK/I 0

V CC

I 1

I 2

I 3

I 4

I 5

I 6

I 7

I 8

GND

I/O 7

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 0

OE/I 9

1 20 19

I 3

I 4

I 5

I 6

I 7

I/O 6

I/O 5

I/O 4

I/O 3

I/O 2

16493D-2

9 10 11 12 13

Note: Pin 1 is marked for orientation.

PIN DESIGNATIONS

CLK = Clock

GND = Ground

16493D-3

= Input

I/O

= Input/Output

= Output Enable

V CC

= Supply Voltage

PALCE16V8 Family

2-37

AMD

ORDERING INFORMATION

Commercial and Industrial Products

AMD programmable logic products for commercial and industrial applications are available with several ordering options. The

order number (Valid Combination) is formed by a combination of:

PAL CE 16 V 8 H -5 P C

FAMILY TYPE

PAL = Programmable Array Logic

OPTIONAL PROCESSING

Blank = Standard Processing

TECHNOLOGY

CE = CMOS Electrically Erasable

NUMBER OF

ARRAY INPUTS

OUTPUT TYPE

V = Versatile

NUMBER OF OUTPUTS

PROGRAMMING DESIGNATOR

Blank = Initial Algorithm

/4 = First Revision

/5 = Second Revision

(Same Algorithm as /4)

POWER

H = Half Power (90 – 125 mA I CC )

Q = Quarter Power (55 mA I CC )

OPERATING CONDITIONS

C = Commercial (0

C to +75

I = Industrial (–40

C to +85

SPEED

-5 = 5 ns t PD

-7 = 7.5 ns t PD

-10 = 10 ns t PD

-15 = 15 ns t PD

-20 = 20 ns t PD

-25 = 25 ns t PD

PACKAGE TYPE

P = 20-Pin Plastic DIP (PD 020)

J = 20-Pin Plastic Leaded Chip

Carrier (PL 020)

S = 20-Pin Plastic Gull-Wing

Small Outline Package (SO 020)

Valid Combinations

PALCE16V8H-5

PALCE16V8H-7

PALCE16V8H-10

PALCE16V8Q-10

PALCE16V8H-15

PALCE16V8Q-15

PALCE16V8Q-20

PALCE16V8H-25

PALCE16V8Q-25

Valid Combinations lists configurations planned

to be supported in volume for this device. Consult

the local AMD sales office to confirm availability of

specific valid combinations and to check on newly

released combinations.

PC, JC

PC, JC, SC, PI, JI

PC, JC, SC

PC, JC, SC, PI, JI

PC, JC

PI, JI

Blank,

PC, JC, SC, PI, JI

PC, JC, PI, JI

2-38

PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com’l)

H-10/15/25, Q-20/25 (Ind)

AMD

FUNCTIONAL DESCRIPTION

The PALCE16V8 is a universal PAL device. It has eight

independently configurable macrocells (MC 0 – MC 7 ).

Each macrocell can be configured as registered output,

combinatorial output, combinatorial I/O or dedicated in-

put. The programming matrix implements a program-

mable AND logic array, which drives a fixed OR logic

array. Buffers for device inputs have complementary

outputs to provide user-programmable input signal po-

larity. Pins 1 and 11 serve either as array inputs or as

clock (CLK) and output enable (OE), respectively, for all

flip-flops.

specification. The design specification is processed by

development software to verify the design and create a

programming file (JEDEC). This file, once downloaded

to a programmer, configures the device according to the

user’s desired function.

The user is given two design options with the

PALCE16V8. First, it can be programmed as a standard

PAL device from the PAL16R8 and PAL10H8 series.

The PAL programmer manufacturer will supply device

codes for the standard PAL device architectures to be

used with the PALCE16V8. The programmer will pro-

gram the PALCE16V8 in the corresponding architec-

ture. This allows the user to use existing standard PAL

device JEDEC files without making any changes to

them. Alternatively, the device can be programmed as

a PALCE16V8. Here the user must use the PALCE16V8

device code. This option allows full utilization of the

macrocell.

Unused input pins should be tied directly to V CC or GND.

Product terms with all bits unprogrammed (discon-

nected) assume the logical HIGH state and product

terms with both true and complement of any input signal

connected assume a logical LOW state.

The programmable functions on the PALCE16V8 are

automatically configured from the user’s design

1 1

1 0

0 0

0 1

Adjacent

Macrocell

1 1

0 X

1 0

V CC

S L0 X

SG1

1 1

0 X

I/O X

1 0

SL1 X

CLK

1 0

1 1

0 X

From

Adjacent

SG1

SL0 X

*In macrocells MC 0 and MC 7 , SG1 is replaced by SG0 on the feedback multiplexer.

16493D-4

PALCE16V8 Macrocell

PALCE16V8 Family

2-39

AMD

Configuration Options

Each macrocell can be configured as one of the follow-

ing: registered output, combinatorial output, combinato-

rial I/O, or dedicated input. In the registered output

configuration, the output buffer is enabled by the OE pin.

In the combinatorial configuration, the buffer is either

controlled by a product term or always enabled. In the

dedicated input configuration, it is always disabled. With

the exception of MC 0 and MC 7 , a macrocell configured

as a dedicated input derives the input signal from an ad-

jacent I/O. MC 0 derives its input from pin 11 (OE) and

MC 7 from pin 1 (CLK).

use the feedback path of MC 7 and pin 11 will use the

feedback path of MC 0 .

Combinatorial I/O in a Non-Registered

Device

The control bit settings are SG0 = 1, SG1 = 1, and SL0 x =

1. Only seven product terms are available to the OR

gate. The eighth product term is used to enable the out-

put buffer. The signal at the I/O pin is fed back to the

AND array via the feedback multiplexer. This allows the

pin to be used as an input.

Because CLK and OE are not used in a non-registered

device, pins 1 and 11 are available as inputs. Pin 1 will

use the feedback path of MC 7 and pin 11 will use the

feedback path of MC 0 .

The macrocell configurations are controlled by the con-

figuration control word. It contains 2 global bits (SG0

and SG1) and 16 local bits (SL0 0 through SL0 7 and SL1 0

through SL1 7 ). SG0 determines whether registers will

be allowed. SG1 determines whether the PALCE16V8

will emulate a PAL16R8 family or a PAL10H8 family de-

vice. Within each macrocell, SL0 x , in conjunction with

SG1, selects the configuration of the macrocell, and

SL1 x sets the output as either active low or active high

for the individual macrocell.

Combinatorial I/O in a Registered Device

The control bit settings are SG0 = 0, SG1 = 1 and SL0 x =

1. Only seven product terms are available to the OR

gate. The eighth product term is used as the output

enable. The feedback signal is the corresponding I/O

signal.

The configuration bits work by acting as control inputs

for the multiplexers in the macrocell. There are four mul-

tiplexers: a product term input, an enable select, an out-

put select, and a feedback select multiplexer. SG1 and

SL0 x are the control signals for all four multiplexers. In

MC 0 and MC 7 , SG0 replaces SG1 on the feedback mul-

tiplexer. This accommodates CLK being the adjacent

pin for MC 7 and OE the adjacent pin for MC 0 .

Dedicated Input Configuration

The control bit settings are SG0 = 1, SG1 = 0 and SL0 x =

1. The output buffer is disabled. Except for MC 0 and MC 7

the feedback signal is an adjacent I/O. For MC 0 and MC 7

the feedback signals are pins 1 and 11. These configu-

rations are summarized in Table 1 and illustrated in

Figure 2.

Table 1. Macrocell Configuration

SG0 SG1 SL0 X Cell Configuration Devices Emulated

Device Uses Registers

0 1 0 Registered Output PAL16R8, 16R6,

16R4

0 1 1 Combinatorial I/O PAL16R6, 16R4

Device Uses No Registers

1 0 0 Combinatorial PAL10H8, 12H6,

Output 14H4, 16H2, 10L8,

12L6, 14L4, 16L2

1 0 1 Input PAL12H6, 14H4,

16H2, 12L6, 14L4,

16L2

1 1 1 Combinatorial I/O PAL16L8

Programmable Output Polarity

The polarity of each macrocell can be active-high or ac-

tive-low, either to match output signal needs or to

reduce product terms. Programmable polarity allows

Boolean expressions to be written in their most compact

form (true or inverted), and the output can still be of the

desired polarity. It can also save “DeMorganizing”

efforts.

Registered Output Configuration

The control bit settings are SG0 = 0, SG1 = 1 and SL0 x =

0. There is only one registered configuration. All eight

product terms are available as inputs to the OR gate.

Data polarity is determined by SL1 x . The flip-flop is

loaded on the LOW-to-HIGH transition of CLK. The

feedback path is from Q on the register. The output

buffer is enabled by OE.

Combinatorial Configurations

The PALCE16V8 has three combinatorial output con-

figurations: dedicated output in a non-registered device,

I/O in a non-registered device and I/O in a registered

device.

Dedicated Output in a Non-Registered

Device

The control bit settings are SG0 = 1, SG1 = 0 and SL0 x =

0. All eight product terms are available to the OR gate.

Although the macrocell is a dedicated output, the feed-

back is used, with the exception of pins 15 and 16. Pins

15 and 16 do not use feedback in this mode. Because

CLK and OE are not used in a non-registered device,

pins 1 and 11 are available as input signals. Pin 1 will

Selection is through a programmable bit SL1 x which

controls an exclusive-OR gate at the output of the AND/

OR logic. The output is active high if SL1 x is 1 and active

low if SL1 x is 0.

2-40

PALCE16V8 Family

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