DS1065.PDF

DS1065

PRELIMINARY

DS1065

EconOscillator/Divider

FEATURES

•

PIN ASSIGNMENT

30 kHz to 100 MHz output frequencies

•

User–programmable on–chip dividers (from 1 – 513)

DALLAS

DS1065

•

User–programmable on–chip prescaler (1, 2, 4)

No external components

• ± 0.5% initial tolerance

• ± 3% variation over temperature and voltage

•

Single 5V supply

12 3

1 23

BOTTOM

VIEW

FREQUENCY OPTIONS

Part No.

Max O/P freq.

PIN DESCRIPTIONS

TO–92

1 I/O

DS1065–100

100 MHz

– Input/Output

DS1065–80

80 MHz

2V CC

– Power Supply

DS1065–66

66 MHz

3 GND

– Ground

DS1065–60

60 MHz

DESCRIPTION

The DS1065 is a fixed frequency oscillator requiring no

external components for operation. Numerous operat-

ing frequencies are possible in the range 30 kHz to 100

MHz through the use of an on–chip programmable pres-

caler and divider.

The DS1065 is shipped from the factory configured for

half the maximum operating frequency. Pre–pro-

grammed devices can be ordered on a custom basis as

DS1065C–xxx.

The DS1065 features a master oscillator followed by a

prescaler and then a programmable divider. The pres-

caler and programmable divider are user–program-

mable with the desired values being stored in nonvola-

tile memory. This allows the user to buy an off the shelf

component and program it on site prior to board produc-

tion. Design changes can be accommodated easily by

simply programming different values into the device (or

reprogramming previously programmed devices).

The DS1065 features a dual–purpose Input/Output pin.

If the device is powered up in Program mode this pin can

be used to input serial data to the on–chip registers.

After a Write command this data is stored in nonvolatile

memory. When the chip is subsequently powered up in

operating mode these values are automatically restored

to the on–chip registers and the Input/Output pin

becomes the oscillator output.

The DS1065 is available in TO–92 (3 LEAD) package,

allowing the generation of a clock signal easily, econom-

ically and using minimal board area.

072998 1/10

•

DS1065

BLOCK DIAGRAM Figure 1

PART NO.

SUFFIX

INTOSC

FREQUENCY

INTERNAL

OSCILLATOR

–100

–80

–66

–60

100 MHz

80 MHz

66 MHz

60 MHz

INTOSC

rst

MSEL

sel

MCLK

PROGRAMMABLE

DIVIDER

÷ N

rst

DIV1

sel

ENABLING

SEQUENCER

POWER

RESET

IN/OUT

I/O

CONT.

SIGNAL PATH

CONTROL PATH

BUS

072998 2/10

DS1065

PIN DESCRIPTIONS

Input/Output Pin (IN/OUT): This pin is the main oscilla-

tor output, with a frequency determined by clock refer-

ence, M and N dividers. Except in programming mode

this pin is always an output and will be referred to as

“OUT”. In programming mode this pin will be referred to

as “IN”.

settings are nonvolatile, the values being stored auto-

matically in EEPROM when the registers are pro-

grammed.

NOTE: The register bits cannot be used to make fre-

quency changes on the fly. Changes can only be made

by powering the device up in “Programming” mode. For

them to be become effective the device must then be

powered down and powered up again in “Operation”

mode.

USER–PROGRAMMABLE REGISTERS

The following registers can be programmed by the user

to determine device operating frequency and mode of

operation. Details of how these registers are pro-

grammed can be found in a later section, in this section

the function of the registers are described. The register

For programming purposes the register bits are divided

into two 9–bit words, the “MUX” word determines mode

prescaler values and the “DIV” word sets the value of

the programmable divider.

072998 3/10

DS1065

MUX WORD Figure 2

(MSB)

(LSB)

MSEL

DIV1

* These bits must be set to the indicated values

DIV1

This bit allows the master clock to be routed directly to

the output (DIV1=1). The N programmable divider is

bypassed so the programmed value of N is ignored. The

frequency of the output (f OUT ) will be INTCLK or

EXTCLK depending on which reference has been

selected. If the Internal clock is selected the M prescaler

is also bypassed (the bit values of MSEL and M are

ignored) so in this case f OUT = INTOSC (which also

equals MCLK and INTCLK). If DIV1=0 the prescaler

and programmable divider function normally.

MSEL

This bit deter mines whether or not the M prescaler is

bypass ed. MSEL=1 will bypass the prescaler.

MSEL=0 will switch in the prescaler (unless overridden

by DIV1=1), with a divide–by number determined by the

M bit.

This bit sets the divide–by number for the prescaler. M

= 0 results in divide–by–4, M=1 results in divide–by–2.

The se tting of this bit is irrelevant if either DIV1=1 or

MSEL=1.

Table 2

DIV1

BIT

MSEL

BIT

OPERATION

INTERNAL OSCILLATOR DIVIDED BY 4*N

INTERNAL OSCILLATOR DIVIDED BY 2*N

INTERNAL OSCILLATOR DIVIDED BY N

INTERNAL OSCILLATOR DIVIDED BY 1

DIV WORD Figure 3

(MSB)

(LSB)

N (9–BITS)

These nine bits determine the value of the program-

mable divider. The range of divisor values is from 2 to

513, and is equal to the programmed value of N plus 2:

POWER–ON RESET

When power is initially applied to the device supply pin,

a power–on reset sequence is executed, similar to that

which occurs when the device is restored from a power–

down condition. This sequence comprises two stages,

first a conventional POR to initialize all on–chip circuitry,

followed by a stabilization period to allow the oscillator

to reach a stable frequency before enabling the output:

Table 3

BIT

VALUES

DIVISOR (N)

VALUE

000000000

000000001

111111111

513

1. Initialize internal circuitry.

2. Enable internal oscillator.

3. Set M and N to maximum values.

4. Wait approximately 1024 cycles of INTOSC for the

oscillator to stabilize.

5. Load M and N programmed values from EEPROM.

6. Enable OUT.

072998 4/10

DS1065

Figure 10

V CC

OUT

t por

t stab

PROGRAMMING

Normally when power is applied to the supply voltage

pin the device will enter its normal operating mode fol-

lowing the power–on reset sequence. However the

device can be made to enter a programming mode if a

pull–up resistor is connected between IN/OUT and the

supply voltage pin, prior to power–up. The method used

for programming is a variant of the 1–Wire TM protocol

used on a number of Dallas Semiconductor products.

HARDWARE

The hardware configuration is shown in the diagram. A

bus master is used to read and write data to the

DS1065’s internal registers. The bus master may have

either an open–drain or TTL–type architecture.

Figure 11

A) OPEN DRAIN

VDD

BUS MASTER

OPEN DRAIN

PORT PIN

DS1065 1–WIRE PORT

DATA

RX = RECEIVE

TX = TRANSMIT

TYP.

MOSFET

B) STANDARD TTL

BUS MASTER

TTL–EQUIVALENT

PORT PINS

VDD

TO IN/OUT

OF DS1065

Programming mode is entered by simply powering up

the DS1065 with a pull–up of approximately 5K W . This

will pull the IN/OUT pin above V IH on power–up and initi-

ate the programming mode, causing the DS1065 to

internally release the IN/OUT pin after t STAB and allow

the pull–up resistor to pull up the pin to the supply rail

and await the Master Tx Reset pulse (see diagram).

in value.

This will cause the IN/OUT pin to remain below V IH on

power–up, resulting in normal operation at the end of

t STAB .

072998 5/10

100

NOTE:

To ensure normal operation any external pull–up

applied to IN/OUT must be greater than 20K

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