74HC299.PDF

M54/74HC299

M54/74HC323

HC299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR

HC323 8 BIT PIPO SHIFT REGISTER WITH SYNCHRONOUS CLEAR

. HIGH SPEED

f MAX = 42 MHz (TYP.) AT V CC =5V

. HIGH NOISE IMMUNITY

V NIH =V NIL =28%V CC (MIN.)

I CC =4

A (MAX.) AT T A =25

. OUTPUT DRIVE CAPABILITY

. SYMMETRICAL OUTPUT IMPEDANCE

B1R

(Plastic Package)

F1R

(Ceramic Package)

. BALANCED PROPAGATION DELAYS

t PLH =t PHL

I OH z

=I OL = 6 mA (MIN.) FOR Q A ,TOQ H ,

I OH z

=I OL = 4 mA (MIN.) FOR Q A ,TOQ H

. WIDE OPERATING VOLTAGE RANGE

. PIN AND FUNCTION COMPATIBLE

WITH 54/74LS299

M1R

(Micro Package)

C1R

(Chip Carrier)

V CC (OPR) = 2 V TO 6 V

ORDER CODES :

M54HCXXXF1R

M74HCXXXM1R

M74HCXXXB1R

M74HCXXXC1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC299/323 are high speed CMOS 8-

BIT PIPO SHIFT REGISTERS (3-STATE) fabri-

cated with silicon gate C 2 MOS technology.

They achieve the high speed operation similar to

equivalent LSTTL while maintaining the CMOS low

power consumption.

These devices have four modes (HOLD, SHIFT

LEFT, SHIFT RIGHT and LOAD DATA). Each mode

is chosen by two function select inputs (S0, S1).

When one or both enable inputs, (G1, G2) are high,

the eight input/output terminals are in the high-

impedance state ; however sequential operation or

clearing of the register is not affected.

Clear function on the HC299 is asynchronous to

CLOCK, while the HC323 is cleared synchronous to

clock.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

NC =

No Internal

Connection

October 1993

1/15

. LOW POWER DISSIPATION

10 LSTTL LOADS FOR QA’ TO QH’

15 LSTTL LOADS FOR QA TO QH

M54/M74HC299/323

INPUT AND OUTPUT EQUIVALENT CIRCUIT

TRUTH TABLE

INPUTS

INPUTS/OUTPUTS

OUTPUTS

MODE

CLEAR

FUNCTION

SELECTED

OUTPUT

CONTROL

CLOCK

SERIAL

A/QA H/QH QA’

QH’

G1 * G2 * (299) (323)

CLEAR

HOLD

QA0 QH0 QA0 QH0

SHIFT

RIGHT

QGn

H H L L L H X QBn H QBn H

H H L L L L X QBn L QBn L

LOAD H H H X X X X a h a h

* When one or both output controls are high, the eight, input/output terminals are in the high impedance state: however sequential operation or clearing

of the register is not affected.

Z : HIGH IMPEDANCE

Qn0 : THE LEVEL OF An BEFORE THE INDICATED STEADY STATE INPUT CONDITIONS WERE ESTABLISHED.

Qnn : THE LEVEL ON Qn BEFORE THE MOST RECENT ACTIVE TRANSITION INDICATED BY

a, h : THE LEVEL OF THE STEADY STATE INPUTS A, H, RESPECTIVELY.

: DON’T CARE

2/15

SHIFT

LEFT

M54/M74HC299/323

LOGIC DIAGRAM (HC299)

3/15

M54/M74HC299/323

LOGIC DIAGRAM (HC323)

4/15

M54/M74HC299/323

TIMING CHART

IEC LOGIC SYMBOLS

HC299

5/15

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