24C02.PDF

Preliminary Information

X24C02

256 x 8 Bit

Serial E 2 PROM

• Internally Organized 256 x 8

• Self Timed Write Cycle

—Typical Write Cycle Time of 5 ms

• 2 Wire Serial Interface

—Bidirectional Data Transfer Protocol

• Four Byte Page Write Operation

—Minimizes Total Write Time Per Byte

• High Reliability

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

• New Hardwire—Write Control Function

DESCRIPTION

The X24C02 is CMOS a 2048 bit serial E 2 PROM,

internally organized 256 x 8. The X24C02 features a

serial interface and software protocol allowing operation

on a simple two wire bus. Three address inputs allow up

to eight devices to share a common two wire bus.

Xicor E 2 PROMs are designed and tested for applica-

tions requiring extended endurance. Inherent data

retention is greater than 100 years. Available in DIP,

MSOP and SOIC packages.

FUNCTIONAL DIAGRAM

(8) V CC

(4) V SS

(7) WC

START CYCLE

H.V. GENERATION

TIMING

& CONTROL

(5) SDA

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

+COMPARATOR

XDEC

E 2 PROM

64 X 32

(6) SCL

LOAD

INC

(3) A 2

(2) A 1

(1) A 0

WORD

ADDRESS

COUNTER

R/W

YDEC

D OUT

DATA REGISTER

D OUT

ACK

3838 FHD F01

Characteristics subject to change without notice

3838-1.2 7/30/96 T0/C3/D1 SH

X24C02

FEATURES

• 2.7V to 5.5V Power Supply

• Low Power CMOS

—Active Current Less Than 1 mA

—Standby Current Less Than 50

X24C02

PIN DESCRIPTIONS

PIN CONFIGURATION

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the

device.

DIP/SOIC/MSOP

A 0

A 1

A 2

V SS

V C C

SCL

SDA

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and

out of the device. It is an open drain output and may be

wire-ORed with any number of open drain or open

collector outputs.

X24C02

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the Guide-

lines for Calculating Typical Values of Bus Pull-Up

Resistors graph.

3838 FHD F02

PIN DESCRIPTIONS

Address (A 0 , A 1 , A 2 )

The address inputs are used to set the least significant

three bits of the seven bit slave address. These inputs

can be static or actively driven. If used statically they

must be tied to V SS or V CC as appropriate. If actively

driven, they must be driven to V SS or to V CC .

Symbol

Description

A 0 –A 2

Address Inputs

SDA

Serial Data

SCL

Serial Clock

Write Control

V SS

Ground

Write Control (WC)

The Write Control input controls the ability to write to the

device. When WC is LOW (tied to V SS ) the X24C02 will

be enabled to perform write operations. When WC is

HIGH (tied to V CC ) the internal high voltage circuitry will

be disabled and all writes will be disabled.

V CC

+5V

3838 PGM T01

X24C02

DEVICE OPERATION

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are re-

served for indicating start and stop conditions. Refer to

Figures 1 and 2.

The X24C02 supports a bidirectional bus oriented pro-

tocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as

the receiver. The device controlling the transfer is a

master and the device being controlled is the slave. The

master will always initiate data transfers and provide the

clock for both transmit and receive operations. There-

fore, the X24C02 will be considered a slave in all

applications.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The X24C02 continuously monitors the SDA and

SCL lines for the start condition and will not respond to

any command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA

CHANGE

3838 FHD F06

X24C02

Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used by the

X24C02 to place the device in the standby power mode

after a read sequence. A stop condition can only be

issued after the transmitting device has released the

bus.

The X24C02 will respond with an acknowledge after

recognition of a start condition and its slave address. If

both the device and a write operation have been se-

lected, the X24C02 will respond with an acknowledge

after the receipt of each subsequent eight bit word.

In the read mode the X24C02 will transmit eight bits of

data, release the SDA line and monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the X24C02

will continue to transmit data. If an acknowledge is not

detected, the X24C02 will terminate further data trans-

missions. The master must then issue a stop condition

to return the X24C02 to the standby power mode and

place the device into a known state.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting

eight bits. During the ninth clock cycle the receiver will

pull the SDA line LOW to acknowledge that it received

the eight bits of data. Refer to Figure 3.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

3838 FHD F07

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

3838 FHD F08

X24C02

DEVICE ADDRESSING

Following the start condition, the X24C02 monitors the

SDA bus comparing the slave address being transmit-

ted with its slave address (device type and state of A 0 ,

A 1 and A 2 inputs). Upon a correct compare the X24C02

outputs an acknowledge on the SDA line. Depending on

the state of the R/W bit, the X24C02 will execute a read

or write operation.

Following a start condition the master must output the

address of the slave it is accessing. The most significant

four bits of the slave are the device type identifier (see

Figure 4). For the X24C02 this is fixed as 1010[B].

Figure 4. Slave Address

WRITE OPERATIONS

DEVICE TYPE

IDENTIFIER

Byte Write

For a write operation, the X24C02 requires a second

address field. This address field is the word address,

comprised of eight bits, providing access to any one of

the 256 words of memory. Upon receipt of the word

address the X24C02 responds with an acknowledge,

and awaits the next eight bits of data, again responding

with an acknowledge. The master then terminates the

transfer by generating a stop condition, at which time the

X24C02 begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress the

X24C02 inputs are disabled, and the device will not

respond to any requests from the master. Refer to

Figure 5 for the address, acknowledge and data transfer

sequence.

A2 A1 A0 R/W

DEVICE

ADDRESS

3838 FHD F09

The next three significant bits address a particular

device. A system could have up to eight X24C02 devices

on the bus (see Figure 10). The eight addresses are

defined by the state of the A 0 , A 1 and A 2 inputs.

The last bit of the slave address defines the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operations is selected.

Figure 5. Byte Write

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

WORD

ADDRESS

DATA

SDA LINE

BUS ACTIVITY:

X24C02

3838 FHD F010

Figure 6. Page Write

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

WORD

ADDRESS (n)

DATA n

DATA n+1

DATA n+3

SDA LINE

BUS ACTIVITY:

X24C02

NOTE: In this example n = xxxx 000 (B); x = 1 or 0

3838 FHD F011

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