Sony IT-B2.pdf

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IT-B2
IT-B2
SERVICE MANUAL
Mexican Model
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IT-B2
SECTION 3
DIAGRAMS
3-1. PRINTED WIRING BOARDS
• Semiconductor
Location
Ref. No. Location
D101
B-2
D102
B-2
D103
B-2
D104
B-2
D105
A-3
D106
A-3
D107
A-3
D108
A-3
D109
B-6
D202
C-2
D205
C-5
D206
C-5
D207
D-5
IC101
A-4
IC201
D-2
Q201
C-1
Q202
C-1
Q204
E-4
Q205
C-4
Q206
B-4
Q207
E-4
Q208
C-4
ZD101
B-3
ZD201
C-2
ZD202
D-5
Note:
• X : parts extracted from the component side.
• : Carbon pattern.
• ¢ : internal component.
• b : Pattern from the side which enables seeing.
4
4
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IT-B2
3-2. SCHEMATIC DIAGRAM • Refer to page 6 for IC Block Diagrams.
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in
and 1 / 4 W or less unless otherwise
specified.
• ¢ : internal component.
• C : panel designation.
• U : B+ Line.
• Power voltage is dc 12V and fed with regulated dc power
supply from J101 with 100
in series.
• Voltage is dc with respect to ground under no-signal
condition.
no mark : OFF HOOK
( ) : ON HOOK
• Voltages are taken with a VOM (Input impedance 10 M W ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
N : RX (from TEL LINE)
O : TX (to TEL LINE)
P : bell
W
5
5
W
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• IC Block Diagrams
IC101 DBL5002
VCC
1
8
OUT
REGULATOR
WITH
HYSTERESIS
AMP
RSL
2
7
HFI
LFI
3
6
HFO
LOW FREQ
OSC
HIGH FREQ
OSC
LFO
4
5
GND
IC201 HM91652B
22
21
20
19
18
17
16
15
14
13
12
PULSE
GENERATOR
DECODER &
DATA LATCH
ROW/COLUMN
PROGRAMMING
COUNTER
D/A
CONVERTER
SAVE
MEMORY
LNB
MEMORY
MEMORY
OUTPUT
INTERFACE
CIRCUIT
KERNEL CONTROL CIRCUIT
INPUT
INTERFACE
CIRCUIT
COLUMN
INTERFACE
CIRCUIT
DIVIDER
ROW
INTERFACE
CIRCUIT
VDD
OSC
VDD
1
2
3
4
5
6
7
8
9
10
11
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