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NM24C02/03 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
February 2000
NM24C02/03 – 2K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The NM24C02/03 devices are 2048 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 1Kbit) of the memory of the NM24C03 can be
write protected by connecting the WP pin to V CC . This section of
memory then becomes unalterable unless WP is switched to V SS .
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.)
Features
Extended operating voltage 2.7V – 5.5V
400 KHz clock frequency (F) at 2.7V - 5.5V
µ
A active current typical
10
µ
A standby current typical
A standby current typical (L)
0.1
µ
µ
A standby current typical (LZ)
IIC compatible interface
– Provides bi-directional data transfer protocol
Schmitt trigger inputs
Sixteen byte page write mode
– Minimizes total write time per byte
Self timed write cycle
Typical write cycle time of 6ms
Hardware Write Protect for upper half (NM24C03 only)
Endurance: 1,000,000 data changes
Data retention greater than 40 years
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
Available in three temperature ranges
- Commercial: 0
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
°
to +70
°
C
to +85C
- Automotive (V): -40 ° to +125 ° C
°
Block Diagram
V CC
V SS
WP
H.V. GENERATION
TIMING &CONTROL
SDA
START
STOP
LOGIC
CONTROL
LOGIC
SCL
SLAVE ADDRESS
REGISTER &
COMPARATOR
XDEC
E 2 PROM
ARRAY
A2
A1
A0
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D IN
DATA REGISTER
D OUT
DS500069-1
© 1998 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
NM24C02/03 Rev. G
200
1
- Extended (E): -40
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Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
A0
1
8
V CC
A1
2
7
NC
A2
3
NM24C02
6
SCL
V SS
4
5
SDA
DS500069-2
See Package Number N08E, M08A and MTC08
Pin Names
A0,A1,A2
Device Address Inputs
V SS
Ground
SDA
Serial Data I/O
SCL
Serial Clock Input
NC
No Connection
V CC
Power Supply
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
A0
1
8
V CC
A1
2
7
WP
A2
3
NM24C03
6
SCL
V SS
4
5
SDA
DS500069-3
See Package Number N08E, M08A and MTC08
Pin Names
A0,A1,A2
Device Address Inputs
V SS
Ground
SDA
Serial Data I/O
SCL
Serial Clock input
WP
Write Protect
V CC
Power Supply
2
www.fairchildsemi.com
NM24C02/03 Rev. G
323060413.018.png 323060413.019.png 323060413.020.png
Ordering Information
NM 24 C XX F LZ E XXX
Letter Description
Package N
8-pin DIP
M8
8-pin SOIC
MT8
8-pin TSSOP
Temp. Range None
0 to 70 ° C
V
-40 to +125 ° C
E
-40 to +85 ° C
Voltage Operating Range Blank
4.5V to 5.5V
L
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1
µ
A Standby Current
SCL Clock Frequency Blank
100KHz
F
400KHz
Density 02
2K
03
2K with Write Protect
C
CMOS Technology
Interface 24
IIC
NM Fairchild Non-Volatile
Memory
3
www.fairchildsemi.com
NM24C02/03 Rev. G
323060413.021.png
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
–65 ° C to +150 ° C
Operating Conditions
Ambient Operating Temperature
NM24C02/03
0 ° C to +70 ° C
All Input or Output Voltages
with Respect to Ground
6.5V to –0.3V
NM24C02E/03E
-40 ° C to +85 ° C
NM24C02V/03V
-40 ° C to +125 ° C
Lead Temperature
(Soldering, 10 seconds)
+300 ° C
Positive Power Supply
NM24C02/03
4.5V to 5.5V
ESD Rating
2000V min.
NM24C02L/03L
2.7V to 5.5V
NM24C02LZ/03LZ
2.7V to 5.5V
DC Electrical Characteristics (2.7V to 5.5V)
Symbol Parameter
Test Conditions
Limits
Units
Min Typ Max
(Note 1)
I CCA
Active Power Supply Current f SCL = 400 KHz
0.2
1.0
mA
f SCL = 100 KHz
I SB
Standby Current
V IN = GND V CC = 2.7V - 5.5V
10
50
µ
A
or V CC
V CC = 2.7V - 5.5V (L)
1
10
µ
A
V CC = 2.7V - 4.5V (LZ)
0.1
1
µ
A
I LI
Input Leakage Current
V IN = GND to V CC
0.1
1
µ A
I LO
Output Leakage Current
V OUT = GND to V CC
0.1
1
µ A
V IL
Input Low Voltage
–0.3
V CC x 0.3
V
V IH
Input High Voltage
V CC x 0.7
V CC + 0.5
V
V OL
Output Low Voltage
I OL = 3 mA
0.4
V
Capacitance T A = +25 ° C, f = 100/400 KHz, V CC = 5V (Note 2)
Symbol
Test
Conditions Max Units
C I/O
Input/Output Capacitance (SDA)
V I/O = 0V
8
pF
C IN
Input Capacitance (A0, A1, A2, SCL)
V IN = 0V
6
pF
C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.
Note 2: This parameter is periodically sampled and not 100% tested.
°
4
www.fairchildsemi.com
NM24C02/03 Rev. G
Note 1: Typical values are T A = 25
323060413.022.png
AC Test Conditions
Input Pulse Levels V CC x 0.1 to V CC x 0.9
Input Rise and Fall Times 10 ns
Input & Output Timing Levels V CC x 0.3 to V CC x 0.7
Output Load
AC Testing Input/Output Waveforms
0.9V CC
0.7V CC
0.3V CC
0.1V CC
DS500069-4
1 TTL Gate and C L = 100 pF
Read and Write Cycle Limits (Standard and Low V CC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min Max Min Max
f SCL
SCL Clock Frequency
100
400
KHz
T I
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V IN
100
50
ns
Pulse width)
t AA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
µ s
t BUF
Time the Bus Must Be Free before
4.7
1.3
µ s
a New Transmission Can Start
t HD:STA
Start Condition Hold Time
4.0
0.6
µ
s
t LOW
Clock Low Period
4.7
1.5
µ
s
t HIGH
Clock High Period
4.0
0.6
µ s
t SU:STA
Start Condition Setup Time
4.7
0.6
µ s
(for a Repeated Start Condition)
t HD:DAT
Data in Hold Time
20
20
ns
t SU:DAT
Data in Setup Time
250
100
ns
t R
SDA and SCL Rise Time
1
0.3
µ s
t F
SDA and SCL Fall Time
300
300
ns
t SU:STO
Stop Condition Setup Time
4.7
0.6
µ s
t DH
Data Out Hold Time
300
50
ns
t WR
Write Cycle Time - NM24C02/03
10
10
ms
(Note 3)
- NM24C02/03L, NM24C02/03LZ
15
15
Note 3 : The write cycle time (t WR ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C02/03 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
t F
t R
t HIGH
t LOW
t LOW
SCL
t SU:STA
t HD:DAT
t SU:DAT
t SU:STO
t HD:STA
SDA
IN
t BUF
t AA
t DH
SDA
OUT
DS500069-5
5
www.fairchildsemi.com
NM24C02/03 Rev. G
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