24C04.pdf

(107 KB) Pobierz
323060434 UNPDF
August 2000
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The FM24C04U/05U devices are 4096 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol. They are designed to
minimize device pin count and simplify PC board layout require-
ments.
The upper half (upper 2Kbit) of the memory of the FM24C05U can
be write protected by connecting the WP pin to V CC . This section of
memory then becomes unalterable unless WP is switched to V SS .
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the FM24C32 or FM24C65 datasheets for more informa-
tion.)
Features
Extended operating voltage 2.7V – 5.5V
400 KHz clock frequency (F) at 2.7V - 5.5V
µ
A active current typical
10
µ
A standby current typical
A standby current typical (L)
0.1
µ
µ
A standby current typical (LZ)
IIC compatible interface
– Provides bi-directional data transfer protocol
Sixteen byte page write mode
– Minimizes total write time per byte
Self timed write cycle
Typical write cycle time of 6ms
Hardware Write Protect for upper half (FM24C05U only)
Endurance: 1,000,000 data changes
Data retention greater than 40 years
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
Available in three temperature ranges
- Commercial: 0 ° to +70 ° C
- Extended (E): -40 ° to +85C
- Automotive (V): -40 ° to +125 ° C
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Block Diagram
V CC
V SS
WP
H.V. GENERATION
TIMING &CONTROL
SDA
START
STOP
LOGIC
CONTROL
LOGIC
SCL
SLAVE ADDRESS
REGISTER &
COMPARATOR
XDEC
E 2 PROM
ARRAY
A2
A1
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D IN
DATA REGISTER
D OUT
© 2000 Fairchild Semiconductor International
1
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
200
1
323060434.026.png 323060434.027.png 323060434.028.png 323060434.029.png 323060434.001.png 323060434.002.png 323060434.003.png 323060434.004.png 323060434.005.png 323060434.006.png 323060434.007.png 323060434.008.png 323060434.009.png 323060434.010.png 323060434.011.png 323060434.012.png 323060434.013.png 323060434.014.png 323060434.015.png 323060434.016.png 323060434.017.png
Connection Diagrams
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC
1
8
V CC
A1
2
7
NC
24C04
A2
3
6
SCL
V SS
4
5
SDA
See Package Number N08E, M08A and MTC08
Pin Names
A1,A2
Device Address Inputs
V SS
Ground
SDA
Serial Data I/O
SCL
Serial Clock Input
NC
No Connection
V CC
Power Supply
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
NC
1
8
V CC
A1
2
7
WP
24C05
A2
3
6
SCL
V SS
4
5
SDA
See Package Number N08E, M08A and MTC08
Pin Names
A1,A2
Device Address Inputs
V SS
Ground
SDA
Serial Data I/O
SCL
Serial Clock input
WP
Write Protect
V CC
Power Supply
NC
No Connection
2
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
323060434.018.png 323060434.019.png 323060434.020.png
Ordering Information
FM 24 C XX U
F
LZ
E XXX
Letter
Description
Package N
8-pin DIP
M8
8-pin SOIC
MT8
8-pin TSSOP
Temp. Range Blank
0 to 70 ° C
V
-40 to +125 ° C
E
-40 to +85 ° C
Voltage Operating Range Blank
4.5V to 5.5V
L
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1
µ
A Standby Current
SCL Clock Frequency Blank
100KHz
F
400KHz
Process U
Ultralite CS100UL
Density 04
4K
05
4K with Write Protect
C
CMOS Technology
Interface 24
IIC
FM
Fairchild Non-Volatile
Memory
3
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
323060434.021.png
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
–65 ° C to +150 ° C
Operating Conditions
Ambient Operating Temperature
FM24C04U/05U
0 ° C to +70 ° C
All Input or Output Voltages
with Respect to Ground
–0.3V to 6.5V
FM24C04UE/05UE
-40 ° C to +85 ° C
FM24C04UV/05UV
-40 ° C to +125 ° C
Lead Temperature
(Soldering, 10 seconds)
+300 ° C
Positive Power Supply
FM24C04U/05U
4.5V to 5.5V
ESD Rating
2000V min.
FM24C04UL/05UL
2.7V to 5.5V
FM24C04ULZ/05ULZ
2.7V to 5.5V
DC Electrical Characteristics (2.7V to 5.5V)
Symbol Parameter
Test Conditions
Limits
Units
Min Typ Max
(Note 1)
I CCA
Active Power Supply Current f SCL = 400 KHz ("F" version)
0.2
1.0
mA
f SCL = 100 KHz
I SB
Standby Current
V IN = GND V CC = 2.7V - 5.5V
10
50
µ
A
(Note 3)
or V CC
V CC = 2.7V - 5.5V (L)
1
10
µ
A
V CC = 2.7V - 4.5V (LZ)
0.1
1
µ
A
I LI
Input Leakage Current
V IN = GND to V CC
0.1
1
µ A
I LO
Output Leakage Current
V OUT = GND to V CC
0.1
1
µ A
V IL
Input Low Voltage
–0.3
V CC x 0.3
V
V IH
Input High Voltage
V CC x 0.7
V CC + 0.5
V
V OL
Output Low Voltage
I OL = 3 mA
0.4
V
Capacitance T A = +25 ° C, f = 100/400 KHz, V CC = 5V (Note 2)
Symbol
Test
Conditions Max Units
C I/O
Input/Output Capacitance (SDA)
V I/O = 0V
8
pF
C IN
Input Capacitance (A0, A1, A2, SCL)
V IN = 0V
6
pF
C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: The "L" and "LZ" versions can be operated in the 2.7V to 5.5V V CC range. However, for a standby current (I SB ) of 1 µ A, the V CC should be within 2.7V to 4.5V.
°
4
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
Note 1: Typical values are T A = 25
323060434.022.png
AC Test Conditions
Input Pulse Levels V CC x 0.1 to V CC x 0.9
Input Rise and Fall Times 10 ns
Input & Output Timing Levels V CC x 0.3 to V CC x 0.7
Output Load
AC Testing Input/Output Waveforms
0.9V CC
0.7V CC
0.3V CC
0.1V CC
1 TTL Gate and C L = 100 pF
Read and Write Cycle Limits (Standard and Low V CC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min Max Min Max
f SCL
SCL Clock Frequency
100
400
KHz
T I
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V IN
100
50
ns
Pulse width)
t AA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
µ s
t BUF
Time the Bus Must Be Free before
4.7
1.3
µ s
a New Transmission Can Start
t HD:STA
Start Condition Hold Time
4.0
0.6
µ
s
t LOW
Clock Low Period
4.7
1.5
µ
s
t HIGH
Clock High Period
4.0
0.6
µ s
t SU:STA
Start Condition Setup Time
4.7
0.6
µ s
(for a Repeated Start Condition)
t HD:DAT
Data in Hold Time
0
0
ns
t SU:DAT
Data in Setup Time
250
100
ns
t R
SDA and SCL Rise Time
1
0.3
µ s
t F
SDA and SCL Fall Time
300
300
ns
t SU:STO
Stop Condition Setup Time
4.7
0.6
µ s
t DH
Data Out Hold Time
300
50
ns
t WR
Write Cycle Time
(Note 4)
4.5V to 5.5V V CC
10
10
ms
2.7V to 4.5V V CC
15
15
Note 4 : The write cycle time (t WR ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
t F
t R
t HIGH
t LOW
t LOW
SCL
t SU:STA
t HD:DAT
t SU:DAT
t SU:STO
t HD:STA
SDA
IN
t BUF
t AA
t DH
SDA
OUT
5
www.fairchildsemi.com
FM24C04U/05U Rev. A.3
323060434.023.png 323060434.024.png 323060434.025.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin