S7-200 Quick Reference.pdf

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S7-200 Quick Reference Information
To help you find information more easily, this section summarizes the following information:
- Special Memory Bits
- Descriptions of Interrupt Events
- Summary of S7-200 CPU Memory Ranges and Features
- High-Speed Counters HSC0, HSC1, HSC2, HSC3, HSC4, HSC5
-
S7-200 Instructions
Table G-1 Special Memory Bits
Special Memory Bits
SM0.0 Always On
SM1.0 Result of operation = 0
SM0.1 First Scan
SM1.1 Overflow or illegal value
SM0.2 Retentive data lost
SM1.2 Negative result
SM0.3 Power up
SM1.3 Division by 0
SM0.4 30 s off / 30 s on
SM1.4 Table full
SM0.5 0.5 s off / 0.5 s on
SM1.5 Table empty
SM0.6 Off 1 scan / on 1 scan
SM1.6 BCD to binary conversion error
SM0.7 Switch in RUN position
SM1.7 ASCII to hex conversion error
489
S7-200 Programmable Controller System Manual
Table G-2 Interrupt Events in Priority Order
Event Number Interrupt Description
Priority Group
Priority in Group
8
Port 0: Receive character
0
9
Port 0: Transmit complete
0
23
Port 0: Receive message complete
Communications
0
Communications
(highest)
24
Port 1: Receive message complete
1
25
Port 1: Receive character
1
26
Port 1: Transmit complete
1
19
PTO 0 complete interrupt
0
20
PTO 1 complete interrupt
1
0
I0.0, Rising edge
2
2
I0.1, Rising edge
3
4
I0.2, Rising edge
4
6
I0.3, Rising edge
5
1
I0.0, Falling edge
6
3
I0.1, Falling edge
7
5
I0.2, Falling edge
8
7
I0.3, Falling edge
9
12
HSC0 CV=PV (current value = preset value)
10
27
HSC0 direction changed
11
Discrete (middle)
28
HSC0 external reset
12
13
HSC1 CV=PV (current value = preset value)
13
14
HSC1 direction input changed
14
15
HSC1 external reset
15
16
HSC2 CV=PV
16
17
HSC2 direction changed
17
18
HSC2 external reset
18
32
HSC3 CV=PV (current value = preset value)
19
29
HSC4 CV=PV (current value = preset value)
20
30
HSC4 direction changed
21
31
HSC4 external reset
22
33
HSC5 CV=PV (current value = preset value)
23
10
Timed interrupt 0
0
11
Timed interrupt 1
1
Timed (lowest)
21
Timer T32 CT=PT interrupt
2
22
Timer T96 CT=PT interrupt
3
490
Discrete (middle)
Timed (lowest)
S7-200 Quick Reference Information Appendix G
Table G-3 Memory Ranges and Features for the S7-200 CPUs
Description
CPU 221
CPU 222
CPU 224
CPU 224XP CPU 226
16384 bytes
24576 bytes
User data size 2048 bytes 2048 bytes 8192 bytes 10240 bytes 10240 bytes
Process-image input register I0.0 to I15.7 I0.0 to I15.7 I0.0 to I15.7 I0.0 to I15.7 I0.0 to I15.7
Process-image output register Q0.0 to Q15.7 Q0.0 to Q15.7 Q0.0 to Q15.7 Q0.0 to Q15.7 Q0.0 to Q15.7
Analog inputs (read only)
4096 bytes
4096 bytes
4096 bytes
4096 bytes
8192 bytes
12288 bytes
12288 bytes
16384 bytes
AIW0 to AIW30 AIW0 to AIW30 AIW0 to AIW62 AIW0 to AIW62 AIW0 to AIW62
Analog outputs (write only)
AQW0 to AQW30 AQW0 to AQW30 AQW0 to AQW62 AQW0 to AQW62 AQW0 to AQW62
Variable memory (V)
VB0 to VB2047 VB0 to VB2047 VB0 to VB8191 VB0 to VB10239 VB0 to VB10239
Local memory (L) 1
LB0toLB63 LB0toLB63 LB0toLB63 LB0toLB63 LB0toLB63
Bit memory (M)
M0.0 to M31.7 M0.0 to M31.7 M0.0 to M31.7 M0.0 to M31.7 M0.0 to M31.7
Special Memory (SM)
Read only
SM0.0 to
SM179.7
SM0.0 to SM29.7
SM0.0 to
SM299.7
SM0.0 to SM29.7
SM0.0 to
SM549.7
SM0.0 to SM29.7
SM0.0 to
SM549.7
SM0.0 to SM29.7
SM0.0 to
SM549.7
SM0.0 to SM29.7
256 (T0 to T255)
T0, T64
T1 to T4, and
T65toT68
T5 to T31, and
T69toT95
T32, T96
T33 to T36, and
T97toT100
T37 to T63, and
T101 to T255
Counters C0 to C255 C0 to C255 C0 to C255 C0 to C255 C0 to C255
High-speed counters HC0 to HC5 HC0 to HC5 HC0 to HC5 HC0 to HC5 HC0 to HC5
Sequential control relays (S) S0.0 to S31.7 S0.0 to S31.7 S0.0 to S31.7 S0.0 to S31.7 S0.0 to S31.7
Accumulator registers
256 (T0 to T255)
T0, T64
T1 to T4, and
T65toT68
T5 to T31, and
T69toT95
T32, T96
T33 to T36, and
T97toT100
T37 to T63, and
T101 to T255
256 (T0 to T255)
T0, T64
T1 to T4, and
T65toT68
T5 to T31, and
T69toT95
T32, T96
T33 to T36, and
T97toT100
T37 to T63, and
T101 to T255
256 (T0 to T255)
T0, T64
T1 to T4, and
T65toT68
T5 to T31, and
T69toT95
T32, T96
T33 to T36, and
T97toT100
T37 to T63, and
T101 to T255
256 (T0 to T255)
T0, T64
T1 to T4, and
T65toT68
T5 to T31, and
T69toT95
T32, T96
T33 to T36, and
T97toT100
T37 to T63, and
T101 to T255
100 ms
On/Off delay
1 ms
10 ms
100 ms
AC0toAC3 AC0toAC3 AC0toAC3 AC0toAC3 AC0toAC3
Jumps/Labels
0to255
0to255
0to255
0to255
0to255
Call/Subroutine
0to63
0to63
0to63
0to63
0to127
Interrupt routines
0to127
0to127
0to127
0to127
0to127
Positive/negative transitions
256
256
256
256
256
PID loops
0to7
0to7
0to7
0to7
0to7
Ports
Port 0
Port 0
Port 0
Port 0, Port 1
Port 0, Port 1
1 LB60 to LB63 are reserved by STEP 7--Micro/WIN, version 3.0 or later.
491
User program size
with run mode edit
without run mode edit
Timers
Retentive on-delay 1 ms
10 ms
S7-200 Programmable Controller System Manual
Table G-4 High-Speed Counters HSC0, HSC3, HSC4, and HSC5
HSC0
HSC3 HSC4
HSC5
Mode
Clk
Direction Reset Clk
Clk
Direction Reset Clk
0
I0.0
I0.1
I0.3
I0.4
1
I0.0
I0.2
I0.3
I0.5
2
3
I0.0
I0.1
I0.3
I0.4
4
I0.0
I0.1
I0.2
I0.3
I0.4
I0.5
5
HSC0
HSC4
Mode
Clk Up Clk Down Reset
Clk Up Clk Down Reset
6
I0.0
I0.1
I0.3
I0.4
7
I0.0
I0.1
I0.2
I0.3
I0.4
I0.5
8
HSC0
HSC4
Mode
Phase A Phase B Reset
Phase A Phase B Reset
9
I0.0
I0.1
I0.3
I0.4
10
I0.0
I0.1
I0.2
I0.3
I0.4
I0.5
11
Mode
HSC0
HSC3
Clk
Clk
12 Q0.0
Q0.1
Table G-5 High-Speed Counters HSC1 and HSC2
Mode
HSC1
HSC2
Clk
Clk Down Reset Start Clk
Direction Reset Start
0
I0.6
I1.2
1
I0.6
I1.0
I1.2
I1.4
2
I0.6
I1.0
I1.1
I1.2
I1.4
I1.5
3
I0.6
I0.7
I1.2
I1.3
4
I0.6
I0.7
I1.0
I1.2
I1.3
I1.4
5
I0.6
I0.7
I1.0
I1.1
I1.2
I1.3
I1.4
I1.5
HSC1
HSC2
Mode
Clk Up Clk Down Reset Start Clk Up Clk Down Reset Start
6
I0.6
I0.7
I1.0
I1.2
I1.3
7
I0.6
I0.7
I1.0
I1.2
I1.3
I1.4
8
I0.6
I0.7
I1.0
I1.1
I1.2
I1.3
I1.4
I1.5
Mode
Phase A Phase B Reset Start
Phase A Phase B Reset Start
9
I0.6
I0.7
I1.2
I1.3
10
I0.6
I0.7
I1.0
I1.2
I1.3
I1.4
11
I0.6
I0.7
I1.0
I1.1
I1.2
I1.3
I1.4
I1.5
492
Mode
Mode
Mode
Mode
Mode
Mode
S7-200 Quick Reference Information Appendix G
Boolean Instructions
LD Bit
LDI Bit
LDN Bit
LDNI Bit
Load
Load Immediate
Load Not
Load Not Immediate
Math, Increment, and Decrement instructions
+I IN1, OUT
+D IN1, OUT
+R IN1, OUT
Add Integer, Double Integer or Real
IN1+OUT=OUT
-- I IN1, OUT
--D IN1, OUT
--R IN1, OUT
Subtract Integer, Double Integer, or
Real
OUT-- IN1=OUT
A Bit
AI Bit
AN Bit
ANI Bit
AND
AND Immediate
AND Not
AND Not Immediate
MUL IN1, OUT
Multiply Integer (16*16-->32)
*I IN1, OUT
*D IN1, OUT
*R IN1, IN2
O Bit
OI Bit
ON Bit
ONI Bit
OR
OR Immediate
OR Not
OR Not Immediate
Multiply Integer, Double Integer, or Real
IN1 * OUT = OUT
DIV IN1, OUT
Divide Integer (16/16-->32)
LDBx IN1, IN2
Load result of Byte Compare
IN1 (x:<, <=,=, >=, >, <>I) IN2
/I IN1, OUT
/D, IN1, OUT
/R IN1, OUT
Divide Integer, Double Integer, or Real
OUT / IN1 = OUT
ABx IN1, IN2
AND result of Byte Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
SQRT IN, OUT
Square Root
OBx IN1, IN2
OR result of Byte Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
LN IN, OUT
Natural Logarithm
LDWx IN1, IN2
Load result of Word Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
EXP IN, OUT
Natural Exponential
SIN IN, OUT
Sine
AWx IN1, IN2
AND result of Word Compare
IN1 (x:<, <=,=, >=, >, <>)I N2
COS IN, OUT
Cosine
TAN I N, OUT
Tangent
OWx IN1, IN2
OR result of Word Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
INCB OUT
INCW OUT
INCD OUT
LDDx IN1, IN2
Load result of DWord Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
Increment Byte, Word or DWord
ADx
IN1, IN2
AND result of DWord Compare
IN1 (x:<, <=,=, >=, >, <>)IN2
DECB OUT
DECW OUT
DECD OUT
Decrement Byte, Word, or DWord
ODx IN1, IN2
OR result of DWord Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
PID TBL, LOOP PID Loop
Timer and Counter Instructions
TON Txxx, PT
TOF Txxx, PT
TONR Txxx, PT
BITIM OUT
CITIM IN, OUT
LDRx IN1, IN2
Load result of Real Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
ARx
IN1, IN2
AND result of Real Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
On-Delay Timer
Off-Delay Timer
Retentive On-Delay Timer
Beginning Interval Timer
Calculate Interval Timer
ORx IN1, IN2
OR result of Real Compare
IN1 (x:<, <=,=, >=, >, <>) IN2
NOT
Stack Negation
EU
ED
Detection of Rising Edge
Detection of Falling Edge
Count Up
Count Down
Count Up/Down
Real Time Clock Instructions
TODR T
TODW T
TODRX T
TODWX T
=
Bit
Assign Value
Assign Value Immediate
=I
Bit
S Bit, N
R Bit, N
SI
Bit, N
Set bit Range
Reset bit Range
Set bit Range Immediate
Reset bit Range Immediate
Read Time of Day clock
Write Time of Day clock
Read Real Time Clock Extended
Set Real Time Clock Extended
Program Control Instructions
END
RI
Bit, N
LDSx IN1, IN2
Load result of String Compare
IN1 (x: =, <>) IN2
AND result of String Compare
IN1 (x: =, <>) IN2
OR result of String Compare
IN1 (x: =, <>) IN2
Conditional End of Program
ASx IN1, IN2
STOP
Transition to STOP Mode
OSx IN1, IN2
WDR
WatchDog Reset (300 ms)
JMP N
LBL N
Jump to defined Label
Define a Label to Jump to
ALD
OLD
And Load
Or Load
CALL N [N1,...]
Call a Subroutine [N1, ... up to 16
optional parameters]
Conditional Return from SBR
LPS
LRD
LPP
LDS N
Logic Push (stack control)
Logic Read (stack control)
Logic Pop (stack control)
Load Stack (stack control)
CRET
FOR INDX,INIT,FINAL
NEXT
For/Next Loop
AENO
And ENO
LSCR N
SCRT N
CSCRE
SCRE
Load, Transition, Conditional End, and
End Sequence Control Relay
DLED IN
Diagnostic LED
493
CTU Cxxx, PV
CTD Cxxx, PV
CTUD Cxxx, PV

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