e00a073.pdf

(116 KB) Pobierz
003008-UK datasheets 10/2000
DS1267
Integrated Circuits
Special Function
DATASHEET 10/2000
DS1267
Integrated Circuits
Special Function
DATASHEET 10/2000
state to prevent any inadvertent changes to the
device shift register.
Once RST has reached a low state, the contents of
the I/O shift register are loaded into the respective
multiplexers for setting wiper position. A new wiper
position will only engage after a RST transition to the
inactive state.
On device power-up the DS1267 wiper positions will
be set at 50% of the total resistance or binary value
1000 0000.
DS1267
Dual Digital Potentiometer Chip
stacked) for an increased total resistance with the
same resolution. For multiple device single processor
environments, the DS1267 can be cascaded or daisy
chained. This feature provides for control of multiple
devices over a single 3-wire bus.
Manufacturer
Dallas Semiconductor.
Internet: http://www.dalsemi.com
Pin description
L0, L1
Application Example
Gameboy Digital Sampling Oscilloscope (GBDSO),
Elektor Electronics October & November 2000
Low End of Resistor
Figure 3. Stacked Configuration.
H0, H1
High End of Resistor
W0, W1
Wiper Terminal of Resistor
the potentiometer-1 wiper position value. Bit 1 will
contain the MSB of the wiper set-ting for poten-
tiometer-1 and bit 8 the LSB for the wiper setting.
Bits 9 through 16 of the I/O shift register contain the
value of the potentiometer-0 wiper position with the
MSB for the wiper position occupying bit 9 and the
LSB bit 16.
Transmission of data always begins with the stack
select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer–0 wiper
position value.
When wiper position data is to be written to the
DS1267, 17 bits (or some integer multiple) of data
should always be transmitted. Transactions which do
not send a complete 17-bits (or multiple) will leave
the register incomplete and possibly an error in the
desired wiper positions.
After a communication transaction has been complet-
ed, the RST signal input should be taken to a low
VB
Substrate Bias Voltage
Stacked Configuration
The potentiometers of the DS1267 can be connected
in series as shown in Figure 3. This is referred to as
the stacked configuration. The stacked configuration
allows the user to double the total end-to-end resis-
tance of the part and the number of steps to 512 (or
9 bits of resolution).
The wiper output for the combined stacked poten-
tiometer will be taken at the S OUT pin, which is the
multiplexed output of the wiper of potentiometer-0
(W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the
S OUT output is governed by the setting of the stack
select bit (bit 0) of the 17-bit I/O shift register. If the
stack select bit has value 0, the multiplexed output,
S OUT , will be that of the potentiometer-0 wiper. If
the stack select bit has value 1, the multiplexed out-
put, S OUT , will be that of the potentiometer-1 wiper.
Features
- Ultra low power consumption, quiet, pumpless
design
- Two digitally controlled, 256-position potentiome-
ters
- Serial port provides means for setting and reading
both potentiometers
- Resistors can be connected in series to provide
increased total resistance
- 14-pin DIP, 16-pin SOIC, 20-pin TSSOP packages
- Resistive elements are temperature compensated to
±0.3 LSB relative linearity
- Standard resistance values:
DS1267-10
SOUT
Stacked Configuration Output
RST
Serial Port Reset Input
DQ
Serial Port Data Input
CLK
Serial Port Clock Input
COUT
Cascade Port Output
VCC
+5 Volt Supply
GND
Ground
NC
No Internal Connection
~10K
Ω
The DS1267 is offered in three standard resistance
values which include 10K, 50K, and 100K ohm ver-
sions.
Available packages for the device include a 14-pin DIP,
16-pin SOIC, and 20-pin TSSOP.
DS1267-50
~50K
Ω
Ω
- Operating Temperature Range – 40°C to +85°C
~100K
Description
The DS1267 consists of two digitally controlled
solid–state potentiometers. Each potentiometer is
composed of 256 resistive sections. Between each
resistive section and both ends of the potentiometer
are tap points which are accessible to the wiper. The
position of the wiper on the resistive array is set by
an 8-bit value that controls which tap point is con-
nected to the wiper output.
Communication and control of the device are accom-
plished via a 3-wire serial port interface. This inter-
face allows the device wiper position to be read or
written.
Both potentiometers can be connected in series (or
Typical application configuration:
inverting variable gain amplifier.
Typical application configuration:
fixed gain attenuator.
DS1267-100
138909138.011.png 138909138.012.png 138909138.013.png 138909138.014.png
DS1267
Integrated Circuits
Special Function
DATASHEET 10/2000
DS1267
Integrated Circuits
Special Function
DATASHEET 10/2000
Recommended DC Operating Conditions (–40ºC to +85ºC; V CC =5.0V
±
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
V CC
4.5
5.5
V
1
Input Logic 1
V IH
2.0
V CC +0.5
V
1
Input Logic 0
V IL
–0.5
+0.8
V
1
Substrate Bias
V B
–5.5
GND
V
1
Resistor Inputs
L, H, W
VB–0.5
V CC +0.5
V
2
DC Electrical Characteristics (–40ºC to +85ºC; V CC =5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Current
I CC
22
650
µ
A
9
Input Leakage
I LI
–1
+1
µ
A
Figure 1. DS1267 Block Diagram
Wiper Resistance
R W
400
1000
Ω
5
Wiper Current
I W
1
mA
Operation
The DS1267 contains two 256-position potentiome-
ters whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17–bit I/O
shift register which is used to store the two wiper
positions and the stack select bit when the device is
powered. A block diagram of the DS1267 is present-
ed in Figure 1.
Communication and control of the DS1267 is accom-
plished through a 3-wire serial port interface that dri-
ves an internal control logic unit. The 3-wire serial
inte r face consists of the three input signals:
RST, CLK, and DQ.
The RST control signal is used to enable the 3-wire
serial port operation of the device. The Chip is
selected when RST is high and RST must be high to
begin any communication to the DS1267. The CLK
signal input is used to provide timing synchronization
for data input and output.
The DQ signal line is used to transmit potentiometer
wiper settings and the stack select bit configuration
to the 17-bit I/O shift register of the DS1267.
Communicatio n with the DS1267 requires the transi-
tion of the RST input from a low state to a high state.
Once the 3–wire port has been activated, data is
entered into the part on the low to high transition of
the CLK signal inputs.
Data written to the DS1267 over the 3-wire serial
inter-face is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both
8–bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift reg-
ister is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit. This bit will be
discussed in the section entitled Stacked Configura-
tion. Bits 1 through 8 of the I/O shift register contain
Output Leakage
I LO
–1
+1
µ
A
Logic 1 Output @ 2.4 Volts
I OH
–1
mA
7
Logic 0 Output @ 0.4 Volts
I OL
4
mA
7
Standby Current
I STBY
22
µ
A
5
Analog Resistor Characteristics (–40ºC to +85ºC; V CC =5.0V
±
10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
End-to-End Resistor Tolerance
–20
+20 %
Absolute Linearity
± 0.75
LSB
3
Relative Linearity
± 0.3
LSB
4
–3 dB Cutoff Frequency
F CUTOFF
Hz
6
Temperature Coefficient
±
800
ppm/ºC
NOTES:
1. All voltages are referenced to ground.
2. Resistor inputs cannot exceed the substrate bias voltage, Vb, in the negative direction.
3. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position.
Device test limits ± 1.6 LSB.
4. Relative linearity is used to determined the change in voltage between successive tap positions.
Device test limits ± 0.5 LSB.
5. Typical values are for TA = 25 ° C and nominal supply voltage.
6. –3 dB cutoff frequency characteristics for the DS1267 depend on potentiometer total resistance:
DS1267-010; 1 MHz, DS1267-050; 200 KHz, DS1267-100; 100 KHz.
7. C OUT is active regardless of the state of RST.
9. See Figure 11 in complete datasheet.
Figure 2. I/O Shift Register.
138909138.001.png 138909138.002.png 138909138.003.png 138909138.004.png 138909138.005.png 138909138.006.png 138909138.007.png 138909138.008.png 138909138.009.png 138909138.010.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin