e991065.pdf

MB501L

AD8307

Integrated Circuits

Special Function, Prescalers

DATASHEET

1/99

Integrated Circuits

Analogue

DATASHEET

1/99

MB501L

Two Modulus Prescaler

Application example

General Coverage Receiver,

Elektor Electronics January & February 1999

AD8307

Low-Cost DC-500 MHz, 92 dB Logarithmic Amplifier

A single supply voltage of 2.7 V to 5.5 V at 7.5 mA is

needed, corresponding to an unprecedented power

consumption of only 22.5 mW at 3 V. A fast-acting

CMOS-compatible control pin can disable the AD8307

to a standby current of under 150 µA.

Manufacturer

Fujitsu. Internet: www.fujitsu.com

Manufacturer

Analog Devices, One Technology Way, P.O. Box 9106,

Norwood, MA 02062-9106, U.S.A.

Internet: www.analog.com.

Product Description

The Fujitsu MB501L is a two modulus prescaler used

in a frequency synthesizer to make a Phase Locked

Loop (PLL). It will divide the input frequency by the

modulus of 64/65 or 128/129 The output level is 1.6V

peak to peak on ECL level.

Pin assignment

Features

- Complete Multistage Logarithmic Amplifier

- 92 dB Dynamic Range: –75 dBm to +17 dBm

To –90 dBm Using Matching Network

- Single Supply of 2.7 V Min at 7.5 mA Typical

- DC-500 MHz Operation,

1 dB Linearity

- Slope of 25 mV/dB, Intercept of –84 dBm

- Highly Stable Scaling Over Temperature

- Fully Differential DC-Coupled Signal Path

- 100 ns Power-Up Time, 150

Features

- High Operating Frequency, Low Power Operation

1.0 GHz at 150mW typ. (MB501)

1.1 GHz at 50 mW typ. (MB501L)

- Pulse Swallow Function

- Wide Operation Temperature T A = –40°C to +85°C

- Stable Output Amplitude V OUT = 1.6 V p-p .

- Complete PLL synthesizer circuit with the Fujitsu

MB87001A, PLL synthesizer IC

- Plastic 8-pin Standard Dual-In-Line Package or space

saving Flat Package

Functional block diagram

A Sleep Current

Input signal amplitude vs. input frequency

Applications

Conversion of Signal Level to Decibel Form

Transmitter Antenna Power Measurement

Receiver Signal Strength Indication (RSSI)

Low Cost Radar and Sonar Signal Processing

Network and Spectrum Analyzers (to 120 dB)

Signal Level Determination Down to 20 Hz

True Decibel AC Mode for Multimeters

Pin configuration

SW MC Divide Ratio

Application Example

RF Decibel Meter, Elektor Electronics January 1999.

1/64

1/65

MB501/501L

1/128

1/129

Product Description (excerpt)

The AD8307 is the first logarithmic amplifier in an 8-

lead (SO-8) package. It is a complete 500-MHz mono-

lithic demodulating logarithmic amplifier based on the

progressive compression (successive detection) tech-

nique, providing a dynamic range of 92 dB to ±3 dB

law-conformance and 88 dB to a tight ±1-dB error

bound at all frequencies up to 100 MHz. It is extremely

stable and easy to use, requiring no significant exter-

nal components.

Note: SW: H = V CC , L = open

MC: H = 2.0 V to V CC

L = GND to 0.8 V

V OUT vs. input level (dBm) at various frequencies.

Block diagram

AD8307

MB501L

Integrated Circuits

Analogue

DATASHEET

1/99

Integrated Circuits

Special Function, Prescalers

DATASHEET

1/99

Recommended Operating Conditions

AD8307 Specifications (V S = +5 V, T A = 25ºC, RL ≥ 1M Ω , unless otherwise noted)

Parameter

Value

Parameter

Symbol

Unit

Conditions

Min Typ Max

Units

Min

Typ

Max

GENERAL CHARACTERISTICS

Input Range (

Supply Voltage

V CC

4.5

5.0

5.5

1 dB Error)

Expressed in dBm re 50

Ω

–72

dBm

Output Current

I O

1.2

Logarithmic Conformance

f ≤ 100 MHz, Central 80 dB

0.3

Ambient Temperature

T A

–40

+85

ºC

f = 500 MHz, Central 75 dB

0.5

Load Capacitance

C L

Logarithmic Slope

Unadjusted 1

mV/dB

vs. Temperature

mV/dB

Logarithmic Intercept

Sine Amplitude; Unadjusted 2

µ V

Equivalent Sine Power in 50

Ω

–87 –84 –77

dBm

vs. Temperature

–88

–76

dBm

Input Noise Spectral Density

Inputs Shorted

1.5

nV/

√

Operating Noise Floor

R SOURCE = 50 Ω /2

–78

dBm

Output Resistance

Pin 4 to Ground

10 12.5

Ω

Internal Load Capacitance

3.5

Response Time

Small Signal, 10%-90%,0 mV-100 mV, C L = 2pF

400

Large Signal, 10%-90%,0 V-2.4 V, C L = 2 pF

500

Upper Usable Frequency 3

500

MHz

Lower Usable Frequency

Input AC-coupled

AMPLIFIER CELL CHARACTERISTICS

Cell Bandwidth

–3 dB

900

MHz

Cell Gain

14.3

INPUT CHARACTERISTICS

DC Common-Mode Voltage

Inputs AC-Coupled

3.2

Common-Mode Range

Either Input (Small Signal)

–0.3 1.6 V S –1

DC Input Offset Voltage 4

R SOURCE ≤

50 Ω

500

µ V

Drift

0.8

mV/ºC

Typical application example

Incremental Input Resistance

Differential

1.1

Ω

Input Capacitance

Either Pin to Ground

1.4

Bias Current

Either Input

POWER INTERFACES

Supply Voltage

2.7

5.5

Supply Current

V ENB ≥

2 V

Disabled

V ENB ≤

1 V

150 750

µ A

NOTES

1 This may be adjusted downward by adding a shunt resistor from the Output to Ground. A 50 k

Ω

resistor will reduce

the nominal slope to 20 mV/dB.

2 This may be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V.

3 See Application on 900 MHz operation.

4 Normally nulled automatically by internal offset correction loop. May be manually nulled by a voltage applied between Pin 3

and Ground; see APPLICATIONS.

Specifications subject to change without notice.

Test circuit

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