87C751.PDF

(201 KB) Pobierz
289310962 UNPDF
INTEGRATED CIRCUITS
83C751/87C751
CMOS single-chip 8-bit microcontrollers
Product specification
1996 Aug 16
IC20 Data Handbook
289310962.020.png 289310962.021.png
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
83C751/87C751
DESCRIPTION
The Philips 83C751/87C751 offers the advantages of the 80C51
architecture in a small package and at low cost.
The 8XC751 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
The 8XC751 contains a 2k
×
8 ROM (83C751) EPROM (87C751), a
8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a
five-source, fixed-priority level interrupt structure, a bidirectional
inter-integrated circuit (I 2 C) serial bus interface, and an on-chip
oscillator.
The on-board inter-integrated circuit (I 2 C) bus interface allows the
8XC751 to operate as a master or slave device on the I 2 C small
area network. This capability facilitates I/O and RAM expansion,
access to EEPROM, processor-to-processor communication, and
efficient interface to a wide variety of dedicated I 2 C peripherals.
×
PIN CONFIGURATIONS
P3.4/A4
P3.3/A3
1
24
V CC
2
23
P3.5/A5
P3.2/A2/A10
3
22
P3.6/A6
P3.1/A1/A9
P3.0/A0/A8
4
CERAMIC
AND
PLASTIC
DUAL
IN-LINE
PACKAGE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
21
P3.7/A7
FEATURES
•
5
20
P1.7/T0/D7
80C51 based architecture
P0.2/V PP
P0.1/SDA/OE–PGM
6
19
P1.6/INT1/D6
•
Inter-Integrated Circuit (I 2 C) serial bus interface
7
18
P1.5/INT0/D5
•
Small package sizes
– 24-pin DIP (300 mil “skinny DIP”)
– 24-pin Shrink Small Outline Package
– 28-pin PLCC
P0.0/SCL/ASEL
8
17
P1.4/D4
RST
9
16
P1.3/D3
X2
10
15
P1.2/D2
X1
11
14
P1.1/D1
•
87C751 available in erasable quartz lid or one-time programmable
plastic packages
V SS
12
13
P1.0/D0
•
Wide oscillator frequency range
416
•
Low power consumption:
– Normal operation: less than 11mA @ 5V, 12MHz
– Idle mode
– Power-down mode
5
PLASTIC
LEADED
CHIP
CARRIER
25
11
19
•
8 ROM (83C751)
2k × 8 EPROM (87C751)
×
12
18
Pin Function
1 P3.4/A4
2 P3.3/A3
3 P3.2/A2/A10
4 P3.1/A1/A9
5 NC*
6 P3.0/A0/A8
7 P0.2/V PP
8 P0.1/SDA/OE-PGM
9 P0.0//SCLASEL
PinFunction
10 NC*
11 RST
12 X2
13 X1
14 V SS
15 P1.0/D0
16 P1.1/D1
17 P1.2/D2
18 P1.3/D3
Pin Function
19 P1.4/ D4
20 P1.5/INT0/D5
21 NC*
22 NC*
23 P1.6/INT1/D6
24 P1.7/T0/D7
25 P3.7/A7
26 P3.6/A6
27 P3.5/A5
28 V CC
•
64 × 8 RAM
•
16-bit auto reloadable counter/timer
•
Fixed-rate timer
•
Boolean processor
•
CMOS and TTL compatible
* DO NOT CONNECT
SU00315
•
Well suited for logic replacement, consumer and industrial
applications
•
LED drive outputs
1996 Aug 16
2
853–0599 17190
64
2k
289310962.022.png
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
83C751/87C751
ORDERING INFORMATION
ROM
EPROM 1
TEMPERATURE RANGE ° C
AND PACKAGE
FREQUENCY
DRAWING
NUMBER
S87C751–1F24
UV
0 to +70, Ceramic Dual In-line Package
3.5 to 12MHz
0586B
S87C751–2F24
UV
–40 to +85, Ceramic Dual In-line Package
3.5 to 12MHz
0586B
S87C751–4F24
UV
0 to +70, Ceramic Dual In-line Package
3.5 to 16MHz
0586B
S87C751–5F24
UV
–40 to +85, Ceramic Dual In-line Package
3.5 to 16MHz
0586B
S83C751–1N24 S87C751–1N24 OTP
0 to +70, Plastic Dual In-line Package
3.5 to 12MHz
SOT222-1
S83C751–2N24 S87C751–2N24 OTP
–40 to +85, Plastic Dual In-line Package
3.5 to 12MHz
SOT222-1
S83C751–4N24 S87C751–4N24 OTP
0 to +70, Plastic Dual In-line Package
3.5 to 16MHz
SOT222-1
S83C751–5N24 S87C751–5N24 OTP
–40 to +85, Plastic Dual In-line Package
3.5 to 16MHz
SOT222-1
S83C751–1A28 S87C751–1A28 OTP
0 to +70, Plastic Leaded Chip Carrier
3.5 to 12MHz
SOT261-3
S83C751–2A28 S87C751–2A28 OTP
–40 to +85, Plastic Leaded Chip Carrier
3.5 to 12MHz
SOT261-3
S83C751–4A28 S87C751–4A28 OTP
0 to +70, Plastic Leaded Chip Carrier
3.5 to 16MHz
SOT261-3
S83C751–5A28 S87C751–5A28 OTP
–40 to +85, Plastic Leaded Chip Carrier
3.5 to 16MHz
SOT261-3
S83C751–1D24 S87C751–1D24 OTP
0 to +70, Shrink Small Outline Package
3.5 to 12MHz
SOT340-1
S83C751–4D24 S87C751–4D24 OTP
0 to +70, Shrink Small Outline Package
3.5 to 16MHz
SOT340-1
NOTE:
1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM.
1996 Aug 16
3
289310962.023.png 289310962.001.png 289310962.002.png
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
83C751/87C751
BLOCK DIAGRAM
P0.0–P0.2
PORT 0
DRIVERS
V CC
I 2 C
CONTROL
V SS
RAM ADDR
REGISTER
RAM
PORT 0
LATCH
ROM/
EPROM
B
REGISTER
ACC
STACK
POINTER
TMP2
TMP1
PROGRAM
ADDRESS
REGISTER
ALU
PCON I2CFG I2STA TCON
I2DAT I2CON IE
TH0 TL0
RTH RTL
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
BUFFER
PSW
PC
INCRE-
MENTER
PROGRAM
COUNTER
RST
TIMING
AND
CONTROL
DPTR
PD
PORT 1
LATCH
PORT 3
LATCH
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
X1
X2
P1.0–P1.7
P3.0–P3.7
SU00316
1996 Aug 16
4
289310962.003.png 289310962.004.png 289310962.005.png 289310962.006.png 289310962.007.png 289310962.008.png 289310962.009.png 289310962.010.png 289310962.011.png 289310962.012.png 289310962.013.png 289310962.014.png 289310962.015.png 289310962.016.png 289310962.017.png
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
83C751/87C751
PIN DESCRIPTIONS
PIN NO.
MNEMONIC
DIP/
SSOP
LCC TYPE
NAME AND FUNCTION
V SS
12
14
I
Circuit Ground Potential
V CC
24
28
I
Supply voltage during normal, idle, and power-down operation.
P0.0–P0.2
8–6
9–7
I/O
Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. Port 0 also serves as the serial I 2 C
interface. When this feature is activated by software, SCL and SDA are driven low in accordance
with the I 2 C protocol. These pins are driven low if the port register bit is written with a 0 or if the I 2 C
subsystem presents a 0. The state of the pin can always be read from the port register by the
program.
To comply with the I 2 C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in
non-I 2 C applications. Port 0 also provides alternate functions for programming the EPROM
memory as follows:
6
7
N/A V PP (P0.2) – Programming voltage input. (See Note 1.)
7
8
I
OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8
9
I
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
7
8
I/O
SDA (P0.1) – I 2 C data.
8
9
I/O
SCL (P0.0) – I 2 C clock.
P1.0–P1.7
13–20 15–20,
23, 24
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I IL ). Port 1 serves to output the addressed EPROM contents in the verify
mode and accepts as inputs the value to program into the selected address during the program
mode . Port 1 also serves the special function features of the 80C51 family as listed below:
18
20
I
INT0 (P1.5): External interrupt.
19
23
I
INT1 (P1.6): External interrupt.
20
24
I
T0 (P1.7): Timer 0 external input.
P3.0–P3.7
5–1,
23–21
6, 4–1,
27–25
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I IL ). Port 3 also functions as the address input for the EPROM memory location to
be programmed (or verified). The 11-bit address is multiplexed into this port as specified by
P0.0/ASEL.
RST
9
11
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V SS permits a power-on RESET using only an external capacitor to
V CC . After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and V PP to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
X1
11
13
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
10
12
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTES:
1. When P0.2 is at or close to 0V it may affect the internal ROM operation. We recommend that P0.2 be tied to V CC via a small pullup
(e.g., 2k
W
).
1996 Aug 16
5
289310962.018.png 289310962.019.png

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin