an61.pdf

Application Note 061

AUGUST 1999

Revision 1.1

10BASE-T PHY

Design and Layout Guide

General Description

Product Line Overview

This application note provides information essential for the

successful design and layout of systems using Level One

10BASE-T PHY transceiver products. The following

topics are covered in this document:

The LXT90X family of Ethernet PHY transceivers

supports 10BASE-T (10T) applications and includes the

following products:

• LXT901/LXT907: Universal 10BASE-T and AUI

PHY Transceivers.

• LXT901A/907A: Universal 10BASE-T and AUI

PHY Transceivers.

• LXT902: Integrated 10BASE-T MAU.

• LXT905: 3.3V Universal 10BASE-T Transceiver.

• LXT908: 3.3V Universal 10BASE-T and AUI

Transceiver.

• LXT944: Universal Quad 10BASE-T Transceiver.

• Product Line Overview.

• Design and Layout Guidelines.

• Grounding Considerations.

• Network Interfaces.

his section summarizes

features, functions, and characteristics of the LXT90X

PHY transceiver product line.

¾T

This section provides

design and layout guidelines to achieve the highest

performance possible from Level One’s 10BASE-T PHY

transceivers. Meeting EMI and ESD requirements and

achieving optimum line performance are accomplished by

following good design practices throughout the entire

design. This section also details placement of power and

ground planes and provides some tips on avoiding the loop-

antenna effect.

Level One’s Ethernet PHY transceivers implement all the

required functions of the Physical Layer Signaling (PLS)

and Media Attchment Unit (MAU) as defined in IEEE

802.3 and are designed for 10BASE-T hub, switch, and

LAN adapter board products.

The LXT901, LXT901A, LXT907, LXT907A, and

LXT908 are extremely robust universal transceivers with a

twisted-pair and AUI port. They function as a PLS-only

device (for use with 10BASE-2 or 10BASE-5 coaxial cable

networks) or as an Integrated PLS/MAU (for use with

twisted-pair networks). Selectable polarity schemes and

control signal timing allow compatibility with most

industry-standard 10BASE-T MAC controllers.

The successful design and

layout of any network product depends on a good

grounding plan. Design considerations for earth, chassis,

and circuit ground are discussed in this section.

The Network Interface section

provides information about the Twisted-Pair Interface and

Attachment Unit Interface (AUI).

The LXT944 integrates four transceivers on a single chip

that drives four independent 10BASE-T twisted-pair

cables.

The Twisted-Pair Interface section details the receive and

transmit circuitry. This section includes magnetics

information, impedance matching, and recommended

termination circuitry.

The LXT901 and LXT907 are operated with a single 5V

power supply. The LXT901A, LXT907A, and LXT908

provide 3.3V low-power operation, ideal for mobile

computing, modems, and NICs. The LXT905 operates at

5V or 3.3V. Functions offered in the PHY family include

Manchester encoding/decoding, receiver squelch and

transmit pulse shaping, jabber, link testing, and reversed

polarity detection/correction. Integrated filters simplify the

design work required for FCC-compliant EMI

performance.

The Attachment Unit Interface (AUI), is briefly discussed,

and a standard AUI circuit diagram is provided.

Refer to www.level1.com for most current information.

)

Product Line Overview

Design and Layout Guidelines

Grounding Considerations

Network Interfaces

10BASE-T PHY Design and Layout Guide

DESIGN AND LAYOUT GUIDELINES

General Guidelines

Good design practices are essential to meet EMI and ESD

requirements, and to achieve maximum line performance.

These practices minimize high-speed digital switching

noise, common-mode noise, and provide shielding between

internal circuits and the environment. Good design

practices apply throughout the entire design and include

the following:

F decoupling capacitors

to reduce high-frequency noise on the power and

ground planes.

• Filter and shield DC-DC converters and oscillators.

• Keep high-speed signals out of the area between the

device and the magnetics.

• Route high-speed signals next to a continuous,

unbroken ground plane.

• Provide termination on all high-speed switching

signals and clock lines.

• Provide impedance matching on long traces to

prevent reflections.

• Fill in unused areas of the signal planes with solid

copper and attach them with vias to a VCC or ground

plane that is not located adjacent to the signal layer.

See signal layer filling diagram in Figure 1 .

• Verify that all components meet application

requirements. Use component listings for reference

only.

• Ensure that the power supply is rated for the load and

that output ripple is minimal (<50 mV).

• Provide ample power planes.

• Keep power and ground noise levels below 50 mV.

• Void the power plane between the magnetics and

RJ-45 connector and at the edge of the card. Use this

region for chassis ground.

• Avoid breaks in the ground plane, especially in areas

where it is shielding high-frequency signals.

• Use bulk capacitors (4.7-10

F) between the power

and ground planes to minimize switching noise,

particularly near high-speed busses.

Power Requirements

LXT901 and LXT907 devices require a single +5V DC

power supply and a single ground reference. Low-power

devices, such as the LXT901A, LXT907A and LXT908,

are supplied by a 3.3V power supply. The LXT905 may be

supplied by either a 3.3V or 5V power supply.

Figure 1: Signal Layer Filling

Layer Name

Plane Fill

Signal 1

Layer 1

Layer 2

Layer 3

Layer 4

Layer 5

Layer 6

VCC

Layers 1 and 3

connected to

VCC

GND Layer

Layers 2 and 4

connected to

GND

Signal 2

Signal 3

VCC

GND

VCC Layer

Signal 4

GND

• Use an ample supply of .01

10BASE-T PHY Design and Layout Guidelines

Differential Signal Layout

Guidelines

• Route differential pairs close together and away from

other signals.

• Keep both traces of each differential pair as identical

to each other as possible.

• Avoid vias and layer changes.

• Keep transmit and receive pairs away from each other.

Run orthogonally, or separate with a ground plane

layer.

• Place all components for the transmit circuit on one

side of the board, and all components for the receive

circuit on the other side of the board.

Use the criteria in Table 1 for evaluating noise levels in the

power and ground planes.

Table 1: Criteria for Noise Levels

Noise Level

Acceptability

Under 50 mV

Acceptable

50 mV to 80 mV

Marginally Acceptable

Above 80 mV

Unacceptable

Bypass and Decoupling Capacitors

Bypass capacitors shunt high-frequency noise from

the power plane to the ground plane and create a

virtual short between power and ground planes at high

frequencies. The noise is shunted to the ground plane

and dispersed.

Place a high-frequency bypass cap (.01

Clock Circuit

The clock circuit should provide a 20 MHz, 100 ppm

digital reference clock to the LXT90X. A crystal oscillator

and clock driver are recommended. Characteristics of the

clock include:

F) between

each VCC pin and its associated ground pin as shown

in Figure 2 .

All bypass capacitors have parasitic inductance

associated with them. This parasitic inductance causes

the capacitors to have a resonance frequency, above

which the capacitors actually become inductive. The

suggested .01

Duty cycle distortion no greater than 40 to 60%.

CMOS voltage levels (V OH > 2.4V).

f cap provides protection up to 140

MHz. Use ample bypass and decoupling capacitors in

a design to help minimize high-frequency noise on the

power and ground planes.

Jitter less than 0.5 ns.

Crystals, oscillators, and DC-to-DC converters can create

significant low- and high-frequency noise and generate

unwanted magnetic fields if not handled correctly. These

types of components should be surrounded with ample

decoupling and bypass capacitors, which can greatly

reduce the impact of unwanted noise and magnetic energy

that can substantially degrade performance.

F typical) liberally

in a design to minimize switching noise. Place a bulk

capacitor near the VCC pin of the LXT90X and

scatter them throughout the entire design to improve

system performance.

F - 10

Noise and Filtering

Power supply ripple and digital switching noise can be

created by:

Figure 2: Power and Ground Decoupling

• Poorly-regulated or over-burdened power supplies.

• Wide data busses (>32-bits) running at a high clock

rate

• DC-to-DC converters.

LXT90X

VCC Plane

VCC

+5V

12.4 k W

.01 m F

RBIAS

GND

Noise created by these sources can be coupled through the

power and ground planes into the transmitter and receiver

and out onto the network. Coupling can occur via the

termination circuits or through the analog power and

ground pins of the LXT90X.

1. Resistor value for RBIAS = 7.5k

for the LXT905 and LXT944.

Bulk Capacitors

Use bulk capacitors (4.7

10BASE-T PHY Design and Layout Guide

Power and Ground Planes

Layout and placement of the power and ground planes are

shown in Figure 3 .

Signal Ground Plane

The signal ground plane is one continuous, unbroken

plane that extends from the magnetics through the rest

of the board. The signal ground plane may be

combined with chassis ground or isolated from it.

For isolation, place a “moat” around the signal ground

plane to separate signal ground from chassis ground.

If the ground planes are combined, an isolation area is

not required.

Power Plane

The power plane is one continuous plane that extends from

the magnetics through the rest of the board. All

components and high-speed signals should be placed in this

area.

Ground Plane

For high-speed communications design, the ground plane

may be conceptually divided into two distinct regions:

Avoiding Loop Antenna Effect

When laying out ground planes, take extra care to avoid

creating a loop antenna effect.

• Run all ground planes as solid square or rectangular

regions.

• Avoid creating loops with ground planes around other

planes. The only exception to this rule is chassis

ground, as shown in Figure 3 .

• Ensure the chassis ground area (running the perimeter

of the board) is voided at some point.

• Ensure the gap of the voided area in chassis ground is

large enough to prevent a loop antenna effect.

• Chassis Ground Plane

• Signal Ground Plane

Chassis Ground Plane

The chassis ground region extends from the front

edge of the board (RJ-45 connectors) to the magnetics

and around the entire perimeter of the board. No

signals should pass through this region except for

external interfaces and LED signals. This region can

be used for a separate chassis ground plane

(connected to the chassis), and connected to cable

shields, unused signals, and safety earth ground.

Figure 3: Power and Ground Placement

Chassis Ground Plane

LEDs

Signal Ground Plane

Power Plane

Magnetic

MAC

SCC

LXT90X

Tie to Safety/

Earth Ground

RJ-45

RAM

Void area to

prevent loop

antenna effect

Optional isolation Area

10BASE-T PHY Grounding Considerations

GROUNDING CONSIDERATIONS

The success of any networking product depends on

beginning with a good electrical grounding plan. The

ground “anchors” the product electrically and provides an

escape path for unwanted electrical and magnetic energy.

This note considers three kinds of ground: earth, chassis,

and circuit.

to protect users from electrocution.

A secondary benefit of this connection is to protect the

electronics from Electro-Static Discharge (ESD), which is

generated primarily by people. A second source of ESD is

long cable connections (>1km), particularly between

buildings. Over these distances, large differences in earth

ground potential can build up

Earth Ground

Earth ground is the absolute reference point for any

electrical system.

as much as 1 or 2 kV,

especially during electrical storms.

Design Considerations

A designer’s capability to control the earth ground

connection varies greatly

from complete to little or

no control. Three possible scenarios are presented

here.

Earth ground is directly available to the designer.

The power supply is often an integrated part of the

design. In many countries, power outlets provide a

specific connection point to earth ground that is

separate from the power connections (“hot” and

“return” leads for power, and a third “safety” lead for

earth ground). In this case, earth ground is brought to

the unit through the power cord and the designer has

complete control.

Earth ground connection is indirectly available to

the designer. The product may be a sub-component

of a product with an integrated power supply. This is

the case for a Network Interface Card (NIC) or

PCMCIA card in a PC or laptop, or for a plug-in card

in a communications product. Here, connections to

earth ground are limited by the overall product design.

Often, electronic connection is made through a

backplane that does not provide a separate earth

ground connection. Connection to earth ground, in

this case, is made mechanically through mounting

brackets or spring fingers.

Earth ground is not available to the designer. The

product may be powered from a DC wall jack. In this

case, design options are very limited.

Electronic devices are generally built to withstand some

amount of ESD. Level One designs its integrated circuits

with a goal of achieving 2kV isolation on all pins. At a

systems level, typical ESD testing requirements go at least

up to 15kV, and the system designer must provide the

difference. At a system level, the solution is to route ESD

currents to chassis ground, then to earth ground, avoiding

the electronics as much as possible. Cable shields and

sometimes the unused wires in the cable can be tied to

chassis ground, which is then tied to earth ground.

Metal Chassis

A metal chassis provides a Farraday shield, which

prevents unwanted electrical and magnetic fields from

emanating from the product. It also protects the

product from outside electrical and magnetic fields.

The chassis is then securely connected to earth

ground.

Non-Metallic Chassis

Many high-volume designs completely dispense with

a metal chassis, preferring instead a molded-plastic

case. Even though the circuit does not have a metal

chassis, a chassis ground connected to earth ground is

still recommended. The chassis ground can be

incorporated into the design of the PCB board as a

separate ground plane and provides ESD protection

and some measure of Farraday shielding.

Chassis Ground

Whenever possible, the designer should provide a

connection between chassis ground and earth ground. The

primary benefit of a connection between the chassis and

earth ground is safety

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