CH22.PDF

The PC Serial Ports

Chapter 22

. For those who need even more serial devices (e.g., to control an electronic bulletin board system

[BBS], you can even buy devices that let you add 16, or more, serial ports to the PC. Since most PCs only

have one or two serial ports, we will concentrate on how to use COM1: and COM2: in this chapter.

Although, in theory, the PC’s original design allows system designers to implement the serial commu-

nication ports using any hardware they desire, much of today’s software that does serial communication

talks directly to the 8250 Serial Communications Chip (SCC) directly. This introduces the same compatibil-

ity problems you get when you talk directly to the parallel port hardware. However, whereas the BIOS

provides an excellent interface to the parallel port, supporting anything you would wish to do by going

directly to the hardware, the serial support is not so good. Therefore, it is common practice to bypass the

BIOS int 14h functions and control the 8250 SCC chip directly so software can access every bit of every

Perhaps an even greater problem with the BIOS code is that it does not support interrupts. Although

software controlling parallel ports rarely uses interrupt driven I/O

, it is very common to find software that

provides interrupt service routines for the serial ports. Since the BIOS does not provide such routines, any

software that wants to use interrupt driven serial I/O will need to talk directly to the 8250 and bypass BIOS

anyway. Therefore, the first part of this chapter will discuss the 8250 chip.

Manipulating the serial port is not difficult. However, the 8250 SCC contains lots of registers and pro-

vides many features. Therefore it takes a lot of code to control every feature of the chip. Fortunately, you

do not have to write that code yourself. The UCR Standard Library provides an excellent set of routines

that let you control the 8250. They even an interrupt service routine allowing interrupt driven I/O. The sec-

ond part of this chapter will present the code from the Standard Library as an example of how to program

each of the registers on the 8250 SCC.

22.1 The 8250 Serial Communications Chip

The 8250 and compatible chips (like the 16450 and 16550 devices) provide nine I/O registers. Certain

upwards compatible devices (e.g., 16450 and 16550) provide a tenth register as well. These registers con-

sume eight I/O port addresses in the PC’s address space. The hardware and locations of the addresses for

these devices are the following:

Table 81: COM Port Addresses

Port

Physical Base Address (in hex)

BIOS variable Containing Physical Address

COM1:

3F8

40:0

COM2:

2F8

40:2

a. Locations 40:4 and 40:6 contain the logical addresses for COM3: and COM4:, but

we will not consider those ports here.

1. Most programs support only COM1: and COM2:. Support for additional serial devices is somewhat limited among various applications.

2. Because many parallel port adapters do not provide hardware support for interrupts.

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The RS-232 serial communication standard is probably the most popular serial communication

scheme in the world. Although it suffers from many drawbacks, speed being the primary one, it use is

widespread and there are literally thousands of devices you can connect to a PC using an RS-232 interface.

The PC supports up to four RS-232 compatible devices using the COM1:, COM2:, COM3:, and COM4:

devices

Chapter 22

Like the PC’s parallel ports, we can swap COM1: and COM2: at the software level by swapping their

base addresses in BIOS variable 40:0 and 40:2. However, software that goes directly to the hardware, espe-

cially interrupt service routines for the serial ports, needs to deal with hardware addresses, not logical

addresses. Therefore, we will always mean I/O base address 3F8h when we discuss COM1: in this chapter.

Likewise, we will always mean I/O base address 2F8h when we discuss COM2: in this chapter.

The base address is the first of eight I/O locations consumed by the 8250 SCC. The exact purpose of

these eight I/O locations appears in the following table:

Table 82: 8250 SCC Registers

I/O Address (hex)

Description

3F8/2F8

Receive/Transmit data register. Also the L.O. byte of the Baud Rate Divisor

Latch register.

3F9/2F9

Interrupt Enable Register. Also the H.O. byte of the Baud Rate Divisor

3FA/2FA

Interrupt Identification Register (read only).

3FB/2FB

Line Control Register.

3FC/2FC

Modem Control Register.

3FD/2FD

Line Status Register (read only).

3FE/2FE

Modem Status Register (read only).

3FF/2FF

Shadow Receive Register (read only, not available on original PCs).

The following sections describe the purpose of each of these registers.

22.1.1 The Data Register (Transmit/Receive Register)

The data register is actually two separate registers: the transmit register and the receive register. You

select the transmit register by writing to I/O addresses 3F8h or 2F8h, you select the receive register by

reading from these addresses. Assuming the transmit register is empty, writing to the transmit register

begins a data transmission across the serial line. Assuming the receive register is full, reading the receive

isters. Please see “The Baud Rate Divisor” on page 1225 and “The Line Control Register” on page 1227 for

more information on the dual use of this I/O location.

22.1.2 The Interrupt Enable Register (IER)

When operating in interrupt mode, the 8250 SCC provides four sources of interrupt: the character

received interrupt, the transmitter empty interrupt, the communication error interrupt, and the status

change interrupt. You can individually enable or disable these interrupt sources by writing ones or zeros

to the 8250 IER (Interrupt Enable Register). Writing a zero to a corresponding bit disables that particular

interrupt. Writing a one enables that interrupt. This register is read/write, so you can interrogate the cur-

rent settings at any time (for example, if you want to mask in a particular interrupt without affecting the

others). The layout of this register is

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The PC Serial Ports

7 6 5 4 3 2 1 0

Data Available Interrupt

Transmitter Empty Interrupt

Error or Break Interrupt

Status Change Interrupt

Unused (should be zero)

Serial Port Interrupt Enable Register (IER)

The interrupt enable register I/O location is also common with the Baud Rate Divisor Register. Please

see the next section and “The Line Control Register” on page 1227 for more information on the dual use of

this I/O location.

22.1.3 The Baud Rate Divisor

The Baud Rate Divisor Register is a 16 bit register that shares I/O locations 3F8h/2F8h and 3F9h/2F9h

with the data and interrupt enable registers. Bit seven of the Line Control Register (see “The Line Control

The Baud Rate Divisor register lets you select the data transmission rate (properly called

, or

bps

, not baud

bits per sec-

Table 83: Baud Rate Divisor Register Values

Bits Per Second

3F9/3F9 Value

3F8/2F8 Value

110

17h

300

80h

600

C0h

1200

60h

1800

40h

2400

30h

3600

20h

4800

18h

9600

0Ch

19.2K

38.4K

56K

3. The term “baud” describes the rate at which tones can change on a modem/telephone line. It turns out that, with normal telephone lines, the

maximum baud rate is 600 baud. Modems that operate at 1200 bps use a different technique (beyond switching tones) to increase the data transfer

rate. In general, there is no such thing as a “1200 baud,” “9600 baud,” or “14.4 kbaud” modem. Properly, these are 1200 bps, 9600bps, and 14.4K bps

modems.

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ond

). The following table lists the values you should write to these registers to control

the transmission/reception rate:

Chapter 22

You should only operate at speeds greater than 19.2K on fast PCs with high performance SCCs (e.g.,

16450 or 16550). Furthermore, you should use high quality cables and keep your cables very short when

running at high speeds.

22.1.4 The Interrupt Identiﬁcation Register (IIR)

The Interrupt Identification Register is a read-only register that specifies whether an interrupt is pend-

ing and which of the four interrupt sources requires attention. This register has the following layout:

7 6 5 4 3 2 1 0

Interrupt pending if zero (no interrupt if one)

Interrupt source:

00: Status change interrupt

01: Transmitter empty interrupt

10: Data available interrupt

11: Error or break interrupt

Always zero.

Interrupt Identification Register (IIR)

Since the IIR can only report one interrupt at a time, and it is certainly possible to have two or more

pending interrupts, the 8250 SCC prioritizes the interrupts. Interrupt source 00 (status change) has the low-

est priority and interrupt source 11 (error or break) has the highest priority; i.e., the interrupt source num-

ber provides the priority (with three being the highest priority).

The following table describes the interrupt sources and how you “clear” the interrupt value in the IIR.

If two interrupts are pending and you service the higher priority request, the 8250 SCC replaces the value

in the IIR with the identification of the next highest priority interrupt source.

Table 84: Interrupt Cause and Release Functions

Priority

ID Value

Interrupt

Caused By

Reset By

Highest

11b

Error or Break

Overrun error, parity error, framing

error, or break interrupt.

Reading the Line Status Register.

Next to

highest

10b

Data available

Data arriving from an external

source in the Receive Register.

Reading the Receive Register.

Next to

lowest

01b

Transmitter

empty

The transmitter finishes sending

data and is ready to accept addi-

tional data.

Reading the IIR (with an interrupt

ID of 01b) or writing to the Data

Lowest

00b

Modem Status

Change in clear to send, data set

ready, ring indicator, or received

line signal detect signals.

Reading the modem status register.

One interesting point to note about the organization of the IIR: the bit layout provides a convenient

way to transfer control to the appropriate section of the SCC interrupt service routine. Consider the follow-

ing code:

al, dx

;Read IIR.

Page 1226

The PC Serial Ports

mov

bl, al

mov

bh, 0

jmp

HandlerTbl[bx]

HandlerTbl word

RLSHandler, RDHandler, TEHandler, MSHandler

When an interrupt occurs, bit zero of the IIR will be zero. The next two bits contain the interrupt source

number and the H.O. five bits are all zero. This lets us use the IIR value as the index into a table of pointers

to the appropriate handler routines, as the above code demonstrates.

22.1.5 The Line Control Register

The Line Control Register lets you specify the transmission parameters for the SCC. This includes set-

ting the data size, number of stop bits, parity, forcing a break, and selecting the Baud Rate Divisor Register

(see “The Baud Rate Divisor” on page 1225) . The Line Control Register is laid out as follows:

7 6 5 4 3 2 1 0

Word length,

00= 5 bits, 01= 6 bits

10= 7 bits, 11= 8 bits.

Stop bits (0=1, 1=2)

Parity enable (0=diabled, 1=enabled)

Parity control

00 = odd parity

01 = even parity

10 = parity is always 1

11 = parity is always 0

Transmit break while 1.

Baud Rate Divisor Latch

Line Control Register (LCR)

. The

start bit is a special signal that informs the SCC (or other device) that data is arriving on the serial line. The

stop bits are, essentially, the absence of a start bit to provide a small amount of time between the arrival of

consecutive characters on the serial line. By selecting two stop bits, you insert some additional time

between the transmission of each character. Some older devices may require this additional time or they

will get confused. However, almost all modern serial devices are perfectly happy with a single stop bit.

Therefore, you should usually program the chip with only one stop bit. Adding a second stop bit increases

transmission time by about 10%.

The parity bits let you enable or disable parity and choose the type of parity. Parity is an error detec-

tion scheme. When you enable parity, the SCC adds an extra bit (the parity bit) to the transmission. If you

select odd parity, the parity bit contains a zero or one so that the L.O. bit of the sum of the data and parity

start bit

, five to eight

data bits

, and one or two

stop bits

Page 1227

The 8250 SCC can transmit serial data as groups of five, six, seven, or eight bits. Most modern serial

communication systems use seven or eight bits for transmission (you only need seven bits to transmit

ASCII, eight bits to transmit binary data). By default, most applications transmit data using eight data bits.

Of course, you always read eight bits from the receive register; the 8250 SCC pads all H.O. bits with zero if

you are receiving less than eight bits. Note that if you are only transmitting ASCII characters, the serial

communications will run about 10% faster with seven bit transmission rather than with eight bit transmis-

sion. This is an important thing to keep in mind if you control both ends of the serial cable. On the other

hand, you will usually be connecting to some device that has a fixed word length, so you will have to pro-

gram the SCC specifically to match that device.

A serial data transmission consists of a

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